Implementation of Fractional Sample Rate Digital Down Converter for Radio Receiver Applications

This paper briefs a novel approach of field-programmable gate array (FPGA) based fractional sample rate digital down converter (FSRDDC) which reduces the sample rate from intermediate frequency (IF) to baseband frequency to meet any practical application. The proposed architecture is highly module and generic that can modify its fractional rate during run time configuration. The proposed fractional rate decimation filter allows frequency translation with a high clock rate and also performs low-pass filtering operations to ensure perfect output. The proposed FSRDDC has been tested on the Kintex-7 Xilinx FPGA target device on an XC7K70T-FBG676. The comparison results show that proposed the scheme is superior to the other similar design in terms of less area, low power consumption, and high speed, so that the design is suitable in digital radio receiver applications.