Asynchronous Gate Signal Driving Method for Reducing Current Imbalance of Paralleled IGBT Modules Caused by Driving Circuit Parameter Difference

Insulated-gate bipolar transistors (IGBTs) always operate in parallel for a large output current in modern high-power converter design. Suppressing dynamic current imbalance of the paralleled IGBTs is crucial for stable operation of converters. Though dynamic current imbalance could be suppressed by the symmetrical power loop design and consistent control signal, there is an inherent parameter difference in the power loop or gate circuit caused by the practical factors such as materials, physical dimensions and installation methods. The inherent difference could be compensated with gate delay control in a certain degree. The voltage and current in the key dynamic phases of IGBT are analyzed to obtain the delay compensation in gate delay control. An asynchronous gate signal driving method based on reference signal selections is proposed to suppress dynamic imbalance of collector current from parallel connected IGBTs, and the implementation of the asynchronous drive is described in brief. By using simulation software, the delay settings and dynamic current imbalance under different parameters discrepancy of drive circuit are obtained. The delay difference from key dynamic phases is calculated as the compensation for balanced dynamic current sharing under two selections of reference signals. Furthermore, the dynamic current distribution in the turn-on and turn-off phases is compensated by the asynchronous drive control. The optimization of asynchronous drive method on dynamic current sharing of paralleled IGBTs is verified by comparing dynamic current imbalance between the system with compensation and the system without compensation.

SECTION I. Introduction

Insulated-gate bipolar transistors (IGBTs) are widely used in modern power electronics due to its characteristics of low on-state voltage, high thermal stability and wide safe operating area. However, the current capacity of a single-tube IGBT can hardly satisfy the needs of large capacity applications due to the limitations of materials and production processes. Direct paralleling of several IGBTs has become an effective solution but dynamic current imbalance occurs [1]. Dynamic current imbalance of paralleled IGBTs is usually reflected in the inconsistency at the moment when collector currents begin to change and the difference of collector current slopes among paralleled IGBTs The devices that turn on fast or turn off slowly during the transients would withstand high current stress which may cause IGBTs’ wear-out or even failure. In the loop composed of the external drive circuit and the internal gate-emitter path of IGBTs, the factors that influence dynamic current sharing of paralleled IGBTs include drive voltage, gate resistance, lead inductance, gate threshold voltage, input capacitance, etc [2], [3]. The inconsistency of the above-mentioned parameters will have varying degrees of influence on dynamic current sharing during different stages in switching processes of paralleled IGBTs. In practical applications, although the unbalanced current caused by the inconsistency of parameters could be suppressed by selecting devices with similar characteristics, modifying drive circuit topologies and derating, the situation will become more complicated with the number of paralleled IGBTs increasing

The closed-loop feedback control method based on the detection of IGBT collector-emitter voltage and collector current [4]–​[8] to adjust the gate voltage or current could be realized for optimizing the switching characteristic of IGBT. For IGBTs in parallel, the idea could also be used as a reference. Though dynamic current imbalance could be suppressed by enhancing the consistency of paralleled IGBTs’ gate voltage [9], a better current sharing may not be achieved if the difference in gate circuits is ignored. By analyzing the voltage-current relationship in the switching processes of IGBTs, dynamic current sharing of paralleled IGBTs could be improved by properly adjusting the drive voltage or the delay of its control signal [10]–​[15].

The algorithm for obtaining gate delay compensation is proposed with the analysis of the stages that have a great impact on IGBTs’ dynamic current sharing during the turn-on and turn-off processes. The “average delay” and the “absolute delay” gate asynchronous drive methods are presented, dynamic current sharing under these two asynchronous driving modes is analyzed and compared.

SECTION II. Asynchronous Drive and the Analysis of the Key Dynamic Phases

A. Principle of Asynchronous Drive Method

Recent publications show that the compensation of delay time $t_{\text {d}}$ to achieve balanced current distribution is highly concerned (see Fig. 1), if the delay time $t_{\text {d}}$ from paralleled IGBTs could be determined in a reliable way. The difference in the gate voltages caused by inconsistence of gate circuits among paralleled IGBTs could be compensated to a certain extent by introducing delays into the control signal of each IGBT. After the delay compensation, the gate voltage or collector current of paralleled IGBTs could be more consistent though the control signals of paralleled IGBTs become asynchronous.

FIGURE 1.

Principle of asynchronous drive method.

The method implemented in this work is based on the indirect determination of $t_{\text {d}}$ from different key phases in switching processes of parallel connected IGBTs, and delay time difference $\Delta t_{\text {d}}$ from the subtraction of $t_{\text {d}}$ is manipulated as the delay compensation during switching transients in order to achieve a simultaneous rise or fall of the collector current $i_{\text {C}}$ . Two ways to determine delay time $t_{\text {d}}$ are obtained by the following theoretical analysis of the key phases in dynamic current sharing.

B. Analysis of the Key Phases in Dynamic Current Sharing

The turn-on and turn-off processes of IGBT are analyzed under the inductive load of Buck circuit. The driving circuit and power loop of four parallel IGBTs at the switching time are shown in Fig. 2. Four IGBTs share the same driving voltage $V_{\text {G}}$ . $R_{\text {Gi}}$ is the gate resistance while $C_{\text {GC}}$ and $C_{\text {GE}}$ are parasitic capacitances. $L_{\text {Ei}}$ is the parasitic inductance between the emitter of the internal chip of the IGBT and the auxiliary emitter terminal. The controlled current source $i_{\text {Ci}}$ is used to correspond to the behavior model of IGBT [16] $v_{\text {GEi}}$ is the gate voltage and $i_{\text {Gi}}$ is the current flowing in the gate. The influence of gate lead inductance is ignored in this research.

FIGURE 2.

Drive circuit and power loop of paralleled IGBTs.

1) Key Phases of the Turn-On Process

The turn-on delay phase: Before the turn-on signal arrives, IGBT is in the off-state where the gate voltage $v_{\text {GEi}}=V_{\text {G,off}}$ (the stable value used to maintain IGBT’s off-state) and collector-emitter voltage equals to DC bus voltage, and diode is manipulated for freewheeling of load current as well. With the arrival of the turn-on signal, the driving voltage $V_{\text {G}}$ whose value turns to $V_{\text {G,on}}$ starts to charge the input capacitance $C_{\text {ies}}$ . The equation of gate circuit and collector current is shown as below \begin{align*} V_{\text {G,on}}=&v_{\text {GE}} + R_{\text {G}} C_{\text {ies}} \frac {\text {d}v_{\text {GE}} }{\text {d}t}\tag{1}\\ i_{\text {C}}=&0\tag{2}\end{align*}

By solving the RC full-response equation, $v_{\text {GE}}$ could be obtained [17], [18]\begin{equation*} v_{\text {GE}} (t)\,\,= V_{\text {G,off}} + (V_{\text {G,on}} - V_{\text {G,off}})\left({1 - e^{ - \frac {t}{C_{\text {ies}} R_{\text {G}}}}}\right)\tag{3}\end{equation*}

Turn-on delay time $t_{\text {d(on)}}$ could be calculated by (3) \begin{equation*} t_{\text {d(on)}} = - C_{\text {ies}} R_{\text {G}} \cdot \ln \frac {V_{\text {G,on}} - V_{\text {GE(th)}} }{V_{\text {G,on}} - V_{\text {G,off}}}\tag{4}\end{equation*}

The collector current rising phase: Collector current tends to increase when gate voltage reaches threshold voltage $V_{\text {GE(th)}}$ . The equation of gate voltage could be presented as (5) considering the impact from parasitic inductance $L_{\text {Ei}}$ . Collector current in linear region could be gained according to behavior model as shown in (6) [19], [20]\begin{align*} V_{\text {G,on}}=&v_{\text {GE}} + R_{\text {G}} C_{\text {ies}} \frac {\text {d}v_{\text {GE}} }{\text {d}t} + L_{\text {Ei}} \frac {\text {d}i_{C} }{\text {d}t}\tag{5}\\ i_{\text {C}}=&\frac {K}{2}(v_{\text {GE}} - V_{\text {GE(th)}})^{2}\tag{6}\end{align*}

It could be obtained by (5) \begin{equation*} L_{\text {Ei}} \cdot \text {d}i_{\text {C}} = V_{\text {G,on}} \text {d}t - R_{\text {G}} C_{\text {ies}} \text {d}v_{\text {GE}} - v_{\text {GE}} \text {d}t\tag{7}\end{equation*}

Approximation is executed after both ends of (7) are integrated \begin{equation*} \Delta i_{\text {C}} = \frac {1}{L_{\text {Ei}} }[V_{\text {G,on}} \Delta t - R_{\text {G}} C_{\text {ies}} \Delta V_{\text {GE}} - V_{\text {GE(ave)}} \Delta t]\tag{8}\end{equation*} where $\Delta V_{\text {GE}}$ and $V_{\text {GE(ave)}}$ are shown in (9) \begin{align*} \begin{cases} \displaystyle \Delta V_{\text {GE}} = V_{\text {GE(pl)}} - V_{\text {GE(th)}} \\ \displaystyle V_{\text {GE(ave)}} = 0.5 \cdot (V_{\text {GE(pl)}} + V_{\text {GE(th)}}) \end{cases}\tag{9}\end{align*}

The variation of collector current during gate voltage rise from $V_{\text {GE(th)}}$ to $V_{\text {GE(pl)}}$ (the plateau voltage) could be approximately calculated by (8).

The collector current from one IGBT in parallel with others could be marked as $I_{\text {C(on)i}}\,\,(i_{\text {C}}=I_{\text {C(on)i}})$ when the total collector current of all paralleled IGBTs comes to the value of the load current $I_{\text {L}}$ . Substituting $I_{\text {C(on)i}}$ into (6) \begin{equation*} V_{\text {GE(pl)}i} = \sqrt {\frac {2I_{C(on)i} }{K}} + V_{\text {GE}(\text {th})i} \quad (i = 1,2,\ldots n)\tag{10}\end{equation*}

In IGBT parallel application, the time $t_{\text {d(cr)}}$ could be obtained where one IGBT’s collector current increases from 0 to $(1/n)I_{\text {L}}$ \begin{equation*} t_{d(cr)} = \frac {\frac {1}{n}I_{L} L_{Ei} + R_{\text {G}} C_{\text {ies}} \Delta V_{\text {GE}} }{V_{\text {G,on}} - V_{\text {GE(ave)}} }\tag{11}\end{equation*}

2) Key Phases of the Turn-Off Process

Turn-off delay phase: the input capacitance begins to discharge after the driving voltage drops from $V_{\text {G,on}}$ to $V_{\text {G,off}}$ . Similarly in the turn-on delay phase, collector-emitter voltage would not increase until the gate voltage falls to the value corresponding to the collector current in linear region where the gate voltage would be held to the plateau voltage $V_{\text {GE(pl)}}$ (it could be regarded as the same value in the turn-off and turn-on processes if the collector current rises little during on-state). It could be calculated in this phase \begin{align*} v_{\text {GE}} (t)\,\,=&V_{\text {G,on}} + (V_{\text {G,off}} - V_{\text {G,on}})\left({1 - e^{ - \frac {t}{C_{\text {ies}} R_{\text {G}} }}}\right)\qquad \tag{12}\\ t_{\text {d(off)}}=&- C_{\text {ies}} R_{\text {G}} \cdot \ln \frac {V_{\text {GE(pl)}} - V_{\text {G,off}} }{V_{\text {G,on}} - V_{\text {G,off}} }\tag{13}\end{align*}

Collector-emitter voltage rising phase: After the gate voltage drops to the voltage corresponding to the collector current of the IGBT in the linear area, the collector-emitter voltage starts to rise and the gate voltage is maintained near the Miller plateau $V_{\text {GE(pl)}}$ . The slope of the collector-emitter voltage could be obtained as (14) shows if the collector current is large \begin{equation*} \frac {\text {d}v_{\text {CE}} }{\text {d}t} = \frac {i_{\text {G}} }{C_{\text {GC}} } = \frac {V_{\text {GE(pl)}} - V_{\text {G,off}} }{R_{\text {G}} C_{\text {GC}} }\tag{14}\end{equation*}

After both ends of (14) are multiplied by “dt”, the deformation can be obtained \begin{equation*} dt = \frac {R_{\text {G}} C_{GC} }{V_{\text {GE(pl)}} - V_{\text {G,off}} }dv_{CE}\tag{15}\end{equation*}

The Miller capacitance $C_{\text {GC}}$ can be regarded as a function of $v_{\text {CE}}$ since it would drop with the increase of the collector-emitter voltage $v_{\text {CE}}$ in this phase. Equation (16) can be gained by integrating two ends of (15) \begin{equation*} \Delta t = \frac {R_{\text {G}} }{V_{\text {GE(pl)}} - V_{\text {G,off}} }\int _{V_{CE(sat)} }^{V_{CE(de)} } {C_{GC} dv_{CE} }\tag{16}\end{equation*} where $V_{\text {CE(dc)}}$ and $V_{\text {CE(sat)}}$ correspond to the values of collector-emitter voltage when it reaches to the DC bus voltage and on-state voltage respectively.

The time $t_{\text {d(vr)}}$ required for the collector-emitter voltage to rise from $V_{\text {CE(sat)}}$ to $V_{\text {CE(dc)}}$ could be obtained from the approximation and simplification of (16), since the variable capacitor $C_{\text {GC}}$ can be respectively regarded as a large capacitance and a small capacitance in the slow rising process and rapid rising process of collector-emitter voltage [21].\begin{align*} \Delta t\approx&\frac {R_{\text {G}} [C_{\text {GC1}} (V_{1} - V_{\text {CE(sat)}}) + C_{\text {GC2}} (V_{\text {CE(dc)}} - V_{1})] }{V_{\text {GE(pl)}} - V_{\text {G,off}} } \\=&t_{\text {d(vr)}}\tag{17}\end{align*}

SECTION III. Implementation of the Asynchronous Drive Method

A. Calculation of Delay Compensation

The delay time for the compensation of dynamic current sharing in paralleled IGBTs could be calculated by using the time information deduced from chapter II. The compensation delay is shown by taking two parallel IGBTs as an example.\begin{align*} \Delta t_{\text {d(on)}}=&\left |{ {t_{\text {d(on)2}} - t_{\text {d(on)1}} } }\right |\tag{18}\\ \Delta t_{\text {d(cr)}}=&\left |{ {t_{\text {d(cr)2}} - t_{\text {d(cr)1}} } }\right |\tag{19}\\ \Delta t_{\text {d(off)}}=&\left |{ {t_{\text {d(off)2}} - t_{\text {d(off)1}} } }\right |\tag{20}\\ \Delta t_{\text {d(vr)}}=&\left |{ {t_{\text {d(vr)2}} - t_{\text {d(vr)1}} } }\right |\tag{21}\end{align*}

B. Determinations of the Delay Times $t_{d}$

1) Determination Based on Parameters Extraction

The calculation of delay times $t_{\text {d}}$ is realizable by extracting the important parameters mentioned in the formula about $t_{\text {d(on)}}$ , $t_{\text {d(cr)}}$ , $t_{\text {d(off)}}$ and $t_{\text {d(vr)}}$ .

Extraction of threshold voltage $V_{\text {GE(th)}}$ , gate capacitance $C_{\text {GE}}$ , Miller capacitance $C_{\text {GC}}$ could be implemented by associating some test topologies and dv/dt characteristic. Gate resistance $R_{\text {G}}$ , parasitic inductance $L_{\text {Ei}}$ and plateau voltage $V_{\text {GE(pl)}}$ can be obtained by manipulating the former parameters such as $V_{\text {GE(th)}}$ and $C_{\text {GE}}$ .

The extraction of the parameter $K$ is critical for the calculation of $V_{\text {GE(pl)}}$ used to gain the compensation delay. The value of $K$ could be obtained by substituting different gate voltages in the linear region and their corresponding collector current values into (6). The deviation could be suppressed by take multiple values around the selected current value into the calculation. The formula for the parameter $K$ is shown in (22).\begin{equation*} K = \frac {2I_{C} }{\left ({{v_{GE} - V_{GE(th)} } }\right)^{2}}\tag{22}\end{equation*}

2) Determination Based on Indirect Measurements

Since delay times $t_{\text {d(on)}}$ and $t_{\text {d(cr)}}$ could be determined by collector-emitter voltage $v_{\text {CE}}$ and induced voltage $L(\textit {di}_{\text {C}}/\textit {dt})$ between auxiliary emitter and power emitter, delay time $t_{\text {d(off)}}$ and $t_{\text {d(vr)}}$ could also be determined by collector-emitter voltage $v_{\text {CE}}$ in both turn-off delay phase and collector-emitter rising phase.

This work is implemented with the former way to determine delay time in key phases while the latter which needs to guarantee the appropriate thresholds of each electrical parameter measured is not investigated

C. Selection About the Reference Signal

At least one of the paralleled IGBT gate control signals needs to be selected as the reference signal to calculate the compensation delay required for the control signals from the remaining IGBTs. There are two ways to choose the reference signal considering that they may have different influence on dynamic current sharing.

Average delay gate asynchronous drive: select the control signal of the IGBT whose current is closest to the average current as a reference signal and introduce delay in other devices for control.

Absolute delay gate asynchronous drive: select the control signal of the IGBT whose current is the smallest or largest as a reference signal and introduce delay in other devices for control.

In conjunction with the above description, the structure of the asynchronous drive could be summarized in five stages shown in Fig. 3.

FIGURE 3.

Structure of the asynchronous drive.

SECTION IV. Current Sharing Characteristics Simulation of Asynchronous Drive

Double pulse simulation circuit is built as Fig. 4 shows where Z2 is IGBT CM400HA-34H from PSpice library. Z1, Z3 and Z4 are IGBT models generated by CM400HA-34H to cause dynamic current imbalance with the change of the relevant parameters of gate. The load current is set to 1200A by adjusting the width of the first pulse. Some simulation parameter settings are shown in Table 1.

TABLE 1 Simulation Parameter Settings

FIGURE 4.

Simulation circuit.

The transfer characteristic curve of CM400HA-34H could be obtained by building test circuit. As a calculation result, $K \approx 105$ . The gate parameters of Z1, Z3 and Z4 are changed to trigger dynamic current imbalance. It is shown in Tables 2(A), (B), the values of threshold voltage $V_{\text {GE(th)}}$ and gate capacitance $C_{\text {GS}}$ as the selected model parameters are changed to gain the corresponding time of the key phases.

TABLE 2A Relevant Parameters’ Settings and Calculated Turn-On Key Phases Delay

TABLE 2B Relevant Parameters’ Settings and Calculated turn-oFF Key Phases Delay

“Parameter value” in Table 2 represents the difference between the set values from Z1, Z3 as well as Z4 and that from Z2. “Turn-on/off key phases delay” in Table 2 corresponds to the time where the paralleled IGBTs accomplish the key phase in the transient process. The compensation delay from Table 3 and Table 4 corresponding to average and absolute delay is calculated by the current distribution (Fig. 5, Fig. 6, Fig. 11 and Fig. 12) and the data from Table 2. The distribution of collector current before and after compensation obtained by simulation is shown in Figs. 516 where Fig. 5, Fig. 6, Fig. 11 and Fig. 12 correspond to the current sharing without compensation, and Fig. 7, Fig. 8, Fig. 13 and Fig. 14 correspond to the current distribution under average delay gate asynchronous drive. The current distribution in Fig. 9, Fig 10, Fig. 15 and Fig. 16 correspond to absolute delay gate asynchronous drive.

TABLE 3 Delay Compensation Under Average Delay Asynchronous Drive

TABLE 4 Delay Compensation Under Absolute Delay Asynchronous Drive

FIGURE 5.

Turn-off current distribution with different $\Delta \text {V}_{\text {GE(th)}}$ (without compensation).

FIGURE 6.

Turn-on current distribution with different $\Delta \text {V}_{\text {GE(th)}}$ (without compensation).

FIGURE 7.

Turn-off current distribution with different $\Delta \text {V}_{\text {GE(th)}}$ (average delay gate asynchronous drive).

FIGURE 8.

Turn-on current distribution with different $\Delta \text {V}_{\text {GE(th)}}$ (average delay gate asynchronous drive).

FIGURE 9.

Turn-off current distribution with different $\Delta \text {V}_{\text {GE(th)}}$ (absolute delay gate asynchronous drive).

FIGURE 10.

Turn-on current distribution with different $\Delta \text {V}_{\text {GE(th)}}$ (absolute delay gate asynchronous drive).

FIGURE 11.

Turn-off current distribution with different $\Delta \text {C}_{\text {GE}}$ (without compensation).

FIGURE 12.

Turn-on current distribution with different $\Delta \text {C}_{\text {GE}}$ (without compensation).

FIGURE 13.

Turn-off current distribution with different $\Delta \text {C}_{\text {GE}}$ (average delay gate asynchronous drive).

FIGURE 14.

Turn-on current distribution with different $\Delta \text {C}_{\text {GE}}$ (average delay gate asynchronous drive).

FIGURE 15.

Turn-off current distribution with different $\Delta \text {C}_{\text {GE}}$ (absolute delay gate asynchronous drive).

FIGURE 16.

Turn-on current distribution with different $\Delta \text {C}_{\text {GE}}$ (absolute delay gate asynchronous drive).

Affected by different setting of threshold voltage $V_{\text {GE(th)}}$ , the paralleled IGBTs with the lowest $V_{\text {GE(th)}}$ (Z1) spend more time in turn-off delay and collector-emitter voltage rising phases but spend less time in turn-on delay and collector current rising phases. Similarly, the time consumed in key phases of other paralleled IGBTs listed in Table 2 could mesh the collector current distribution shown in Fig. 5 and Fig. 6.

The paralleled IGBT with larger gate capacitance (Z4) would spend more time in all key phases of turn-on and turn-off transients. It corresponds well to the current sharing in Fig. 11 and Fig. 12 and the delay time calculated in Table 2.

The control signal of Z3 is regarded as the reference signal for average delay gate asynchronous drive with different threshold voltage $V_{\text {GE(th)}}$ in each paralleled branch. The control signals of Z2 (turn-on) and Z3 (turn-off) are regarded as the reference signal for average delay gate asynchronous drive with different input capacitance $C_{\text {GE}}$ in each paralleled branch. For absolute delay gate asynchronous drive, the control signal of Z4 is selected as the reference signal where threshold voltage $V_{\text {GE(th)}}$ is different in every paralleled IGBT. Furthermore, the control signals of Z4 and Z1 are respectively chosen as the reference signal for the turn-on and turn-off compensation.

After the selection of the reference signal and the calculation about delay compensation under average/absolute asynchronous drive, the consistency of collector current rising comes to a high level and the difference of collector current both decreases under two types of asynchronous drive (Fig. 7 to Fig. 10). In Fig. 13 and Fig. 15, it could be observed that an improvement of collector current rising consistency occurs under average/absolute asynchronous drive compared with the uncompensated situation. The imbalance of current sharing is smaller in Fig. 14 and Fig. 16 than that of the uncompensated.

The current imbalance [22]–​[26] $\delta $ and imbalance improvement factor $\Delta \delta $ are defined as shown in (23) and (24) where $I_{\text {Cmax}}$ and $I_{\text {Cmin}}$ correspond to the maximum and minimum values of collector current flowing through the four paralleled IGBTs. $I_{\text {Ctot}}$ is the value of total current when $I_{\text {Cmax}}$ and $I_{\text {Cmin}}$ appear. In Table 5 and Table 6, $\delta $ and $\delta $ ’ respectively correspond to the uncompensated current imbalance and compensated current imbalance.\begin{align*} \delta=&\frac {I_{\text {Cmax}} - I_{\text {Cmin}} }{I_{\text {Ctot}} }\tag{23}\\ \Delta \delta=&\frac {\delta - {\delta }'}{\delta }\tag{24}\end{align*}

TABLE 5 Current Unbalance and its Optimization Factors During Switching Process (Average Delay Gate Asynchronous Drive)

TABLE 6 Current Unbalance and its Optimization Factors During Switching Process (Absolute Delay Gate Asynchronous Drive)

Dynamic current sharing is improved by average and absolute delay gate asynchronous drive under two different types of drive circuit parameter settings shown in Table 5 and Table 6 (all imbalance improvement factors $\Delta \delta $ are above 30%). Under the same parameter setting, the improvement for the current imbalance in the turn-on process is close to that in the turn-off process.

The current imbalance $\delta $ and imbalance improvement factor $\Delta \delta $ in average and absolute delay gate asynchronous drive are respectively much closer to those in absolute delay gate asynchronous drive for the same parameter setting, which means that the difference in drive circuit is compensated in the same degree. The performance indicates that the time of the key phase from the switch process is adjusted to the same degree under different reference signals.

In the view of the fact that average delay and absolute delay gate asynchronous drive almost obtain the same suppression effect on dynamic current imbalance the extra simulation with different settings of $V_{\text {GE(th)}}$ and $C_{\text {GE}}$ only under average delay gate asynchronous drive is carried out for further verification. The values of the current imbalance $\delta $ and $\delta $ ’ are presented in Fig. 17 and Fig. 18 and the imbalance improvement factor $\Delta \delta $ calculated from the simulation results is shown in Fig. 19 and Fig. 20 In the following figures and discussion, $\Delta V'_{\text {GE(th)}}$ is the difference between the maximum and minimum of $V_{\text {GE(th)}}$ from four paralleled IGBTs. The meaning of $\Delta C'_{\text {GE}}$ is similar to this.

FIGURE 17.

Distribution of $\delta $ with different $\Delta \text {V}'_{\text {GE(th)}}$ (average delay gate asynchronous drive).

FIGURE 18.

Distribution of $\delta $ with different $\Delta \text {C}'_{\text {GE}}$ (average delay gate asynchronous drive).

FIGURE 19.

Distribution of $\Delta \delta $ with different $\Delta \text {V}'_{\text {GE(th)}}$ (average delay gate asynchronous drive).

FIGURE 20.

Distribution of $\Delta \delta $ with different $\Delta \text {C}'_{\text {GE}}$ (average delay gate asynchronous drive).

In Fig. 17, though the imbalance improvement factor $\Delta \delta $ under different $V_{\text {GE(th)}}$ is higher than 40%, it does not vary monotonically with $\Delta V'_{\text {GE(th)}}$ In other words, the values of $\Delta \delta $ always fluctuate when $\Delta V'_{\text {GE(th)}}$ rises from 1% to 10% during both turn-on and turn-off transients It could be observed that $\Delta \delta $ of turn-on obtains a higher value while $\Delta \delta $ of turn-off reaches a lower value. It means that the effect for suppressing dynamic imbalance under gate asynchronous drive may not achieve the optimum in both turn-on and turn-off stages. In spite of this, the effective improvement of collector sharing could be achieved under the practical and appropriate gate delay settings.

Compared with the distribution of imbalance improvement factor $\Delta \delta $ under different $V_{\text {GE(th)}}$ settings, $\Delta \delta $ within different $C_{\text {GE}}$ settings almost reaches much higher values. It is worth noting that $\Delta \delta $ of turn-on transient reaches the maximum value among the presented simulation results under 1% of $\Delta C'_{\text {GE}}$ while $\Delta \delta $ of turn-off transient drops to −64% The occurrence of the negative value of $\Delta \delta $ coresponding to 1% $\Delta C'_{\text {GE}}$ indicates that gate asynchronous drive may cause an unexpected increase of current imbalance $\delta $ The compensation delay of each IGBT is too close to adjust dynamic current sharing Compensated current imbalance $\delta $ ’ of this situation is still lower than 2% it means that the impact caused by compensation failure could be ignored to some extent Similar to the distribution under different $V_{\text {GE(th)}}$ settings, $\Delta \delta $ fluctuate when $\Delta C'_{\text {GE}}$ rise from 1% to 10% with the phenomenon that $\Delta \delta $ from turn-on and turn-off transients under the same $\Delta C'_{\text {GE}}$ settings could not reach the maximum value respectively.

SECTION V. Experimental Validations of the Asynchronous Drive Method

It is necessary to verify the asynchronous drive method by carrying out experiment. Since output characteristics of drivers should be consistent before IGBT paralleling test, adjustment of delay time needs to be completed. Then, the parameters of gate circuits of each IGBT module are extracted to calculate delay compensation for asynchronous drive. Furthermore, gate voltage and collector current distribution before and after the compensation is established.

A. Adjustment of Drivers and Parameters Extraction of Gate Circuits

The output characteristics of drivers about four IGBT modules are observed without driving IGBT gate circuits. In Fig. 21 and Fig. 22, the output voltage of drivers during turn-on and turn-off processes is presented. It could be found that the output voltage of driver 2 (Channel 2) lags behind others (Channel 1: driver 1, Channel 3: driver 3, Channel 4: driver 4) in turn-off process clearly. In addition, the output voltage of driver 3 and driver 4 also lag behind driver 1 approximately 30ns.

FIGURE 21.

Output characteristics of drivers in turn-off process (Channel 1: driver 1, Channel 2: driver 2, Channel 3: driver 3, Channel 4: driver 4).

FIGURE 22.

Output characteristics of drivers in turn-on process (Channel 1: driver 1, Channel 2: driver 2, Channel 3: driver 3, Channel 4: driver 4).

By introducing delay time to driver 1, driver 3 and driver 4, the consistency of four drivers is ensured. Then, gate voltage distribution of IGBT modules after adjustment is shown in Fig. 23 and 24.

FIGURE 23.

Gate voltage distribution of IGBT modules in turn-off process (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).

FIGURE 24.

Gate voltage distribution of IGBT modules in turn-on process (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).

The parameters of gate circuit is extracted respectively by low power, high power test and consulting data sheet. The basic data of the test bench are summarized in Table 7. The data of gate circuit parameters which will be used in calculation of delay time for compensation are listed in Table 8.

TABLE 7 IGBT Test Bench Data

TABLE 8 Parameters of IGBT Gate Circuit

In Table 8, parameter $K$ is calculated by transfer characteristics of the data sheet of 2MBI200U4H-120. Since it is difficult to extract the parameter $L_{\text {Ei}}$ , the value of $L_{\text {Ei}}$ is estimated with the package composed of two chips that have eight bonding wires. The value of $R_{\text {G,on}}$ and $R_{\text {G,off}}$ is gained by extracting the resistance inside and outside gate.

B. Calculation of Delay Compensation and Double Pulse Test With Four Parallel Connected IGBTS

Associated with the equations in section II, the parameters of gate circuit from four IGBT modules could be turned into the time information. In Table 9, the time information of key phases of the turn-on and turn-off transients is listed to calculate delay compensation shown in Table 10. In view of practicability, absolute delay gate asynchronous drive is used in the experiment. Gate control signal of the module which turn on/off slowly is selected as the reference signal.

TABLE 9 Calculation Results of Key Phase Delay

TABLE 10 Calculation Results of Compensation Delay

Gate control signals of module 2 and module 4 are respectively selected as the reference signals of turn-on process and turn-off process. In consideration of the clock period of CPLD from driver ($f_{\text {clock}}=16\text {MHz}$ ), the calculation results of compensation delay is adjusted to fit the practical situation.

Fig. 25 shows a buck converter with six paralleled IGBT half-bridge modules 2MBI200U4H-120 within 200V 400A. In this research, the number of modules is limited to four. The driving signal distribution of paralleled IGBT modules without compensation is shown in Fig. 26, and Fig. 27 shows the driving signal distribution of paralleled IGBT modules with compensation.

FIGURE 25.

IGBT modules paralleling experimental setup.

FIGURE 26.

The driving signal distribution of IGBT modules, without compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).

FIGURE 27.

The driving signal distribution of IGBT modules, with compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).

In the turn-off process before compensation, the distribution of gate voltage and Collector current about four paralleled IGBT modules are shown in Fig. 28 to Fig. 29.

FIGURE 28.

Gate voltage distribution of IGBT modules in turn-off process, without compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).

FIGURE 29.

Collector current distribution of IGBT modules in turn-off process, without compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).

After compensation, the distribution of gate voltage and Collector current about four paralleled IGBT modules are shown in Fig. 30 to Fig. 31. Although $i_{\text {C2}}$ and $i_{\text {C4}}$ become closer by adding the compensation delay to the driver 2 and driver 3, larger current is beard within module 3 instead (Fig. 29 and Fig. 31).

FIGURE 30.

Gate voltage distribution of IGBT modules in turn-off process, with compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).

FIGURE 31.

Collector current distribution of IGBT modules in turn-off process, with compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).

In the turn-on process before compensation, the distribution of gate voltage and Collector current about four paralleled IGBT modules are shown in Fig. 32 to Fig. 33.

FIGURE 32.

Gate voltage distribution of IGBT modules in turn-on process, without compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).

FIGURE 33.

Collector current distribution of IGBT modules in turn-on process, without compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).

Compared with the collector current distribution without compensation (Fig. 33) in the turn-on transient, the collector current consistency of four paralleled IGBT modules is improved (Fig. 35) as expected. After introducing different delays respectively in the gate control signals of module 1, 3 and 4 (Fig. 34), the moment when their collector currents begin to change and the slopes of their collector current are closer to those of module 2.

FIGURE 34.

Gate voltage distribution of IGBT modules in turn-on process, with compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).

FIGURE 35.

Collector current distribution of IGBT modules in turn-on process, with compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).

According to (23) and (24), the current imbalance $\delta $ and imbalance improvement factor $\Delta \delta $ are calculated as shown in Table 11.

TABLE 11 Current Unbalance and its Optimization Factors During Switching Process (Absolute Delay Gate Asynchronous Drive)

Contrasted with the simulation results, though the current imbalance in the turn-on transient is suppressed by asynchronous drive method ($\Delta \delta $ up to 30.33%), the distribution of collector current in the turn-off transient is not compensated well as expected. In addition to the difference in gate circuit parameters, the asymmetry of power loop may play a negative role in dynamic sharing in the practical test while the impedance distribution of power loop in simulation circuit is ideal. Because of other modules’ faster turn-off, the collector current of module 4 begin to rise in the turn-off process. Due to the structure of power loop, the parasitic inductance of module 4 which could cause an induced voltage between the gate and auxiliary emitter is larger than that of other IGBT modules. As a consequence, an abnormal peak consists of the actual gate voltage and induced voltage appeared in the turn-off process of module 4 (Fig. 28 and Fig. 30).

SECTION VI. Conclusion

Based on the analysis of the key phases in the turn-on and turn-off processes, average/absolute delay gate asynchronous drive is proposed through the choice of the reference signal. The PSpice simulation of Buck circuit with four paralleled IGBTs is built to cause dynamic current imbalance by setting two types of difference in gate circuit. Then, the comparison of the current imbalance $\delta $ and imbalance improvement factor $\Delta \delta $ is made as the evidence of the effectiveness of the gate asynchronous driving control method In addition, a wider range of simulations with different $V_{\text {GE(th)}}$ and $C_{\text {GE}}$ settings corresponding to $\Delta V'_{\text {GE(th)}}$ and $\Delta C'_{\text {GE}}$ is implemented. The effectiveness of asynchronous gate Signal driving method is discussed by showing current imbalance $\delta $ in uncompensated situations and the compensated Furthermore the corresponding calculation results of imbalance improvement factor $\Delta \delta $ under two parameter settings are presented to describe the limitation of the gate asynchronous driving control method.

After the adjustment of drivers’ consistency and extraction of gate circuit parameters, the calculation of compensation delay is achieved. A four paralleled IGBT half-bridge modules experimental setup is established to verify asynchronous driver method, the experimental results show an improvement in dynamic current sharing in the turn-on transient. The unexpected unbalanced current appeared in the turn-off transient is noteworthy to weigh the asymmetry of power loop design and asynchronous gate signal driving method The paralleling of IGBT modules is always applied in high-voltage and large-power occasion where the switching frequency of single IGBT module could hardly exceed 10kHz, and the switching frequency of power devices is far below 1kHz in the application of high voltage great power frequency converters, traction converters for rail transit, wind power converters, HVDC substation, etc. The moments where asynchronous gate signal driving method acts on the paralleled IGBT modules are turn-on process and turn-off process. The time of turn-on process and turn-on process is relatively short compared to the time of on-state regardless of how high the switching frequency of IGBT module is (see in Fig. 3 in this response). So the presented method could complete the compensation task under the switching frequency where all IGBT modules operate normally. The practical compensation delay for paralleled IGBT modules is set under the certain operating conditions by adjusting the delay of driving signal, and the driving circuits would introduce the compensation into each paralleled branch. Under the normal switching frequency for paralleled IGBT modules, the real-time calculation of compensation delay is not necessary for the control system, in other words, there is no strict requirements for operation speed of control system to complete compensation.