Introduction
Insulated-gate bipolar transistors (IGBTs) are widely used in modern power electronics due to its characteristics of low on-state voltage, high thermal stability and wide safe operating area. However, the current capacity of a single-tube IGBT can hardly satisfy the needs of large capacity applications due to the limitations of materials and production processes. Direct paralleling of several IGBTs has become an effective solution but dynamic current imbalance occurs [1]. Dynamic current imbalance of paralleled IGBTs is usually reflected in the inconsistency at the moment when collector currents begin to change and the difference of collector current slopes among paralleled IGBTs The devices that turn on fast or turn off slowly during the transients would withstand high current stress which may cause IGBTs’ wear-out or even failure. In the loop composed of the external drive circuit and the internal gate-emitter path of IGBTs, the factors that influence dynamic current sharing of paralleled IGBTs include drive voltage, gate resistance, lead inductance, gate threshold voltage, input capacitance, etc [2], [3]. The inconsistency of the above-mentioned parameters will have varying degrees of influence on dynamic current sharing during different stages in switching processes of paralleled IGBTs. In practical applications, although the unbalanced current caused by the inconsistency of parameters could be suppressed by selecting devices with similar characteristics, modifying drive circuit topologies and derating, the situation will become more complicated with the number of paralleled IGBTs increasing
The closed-loop feedback control method based on the detection of IGBT collector-emitter voltage and collector current [4]–[8] to adjust the gate voltage or current could be realized for optimizing the switching characteristic of IGBT. For IGBTs in parallel, the idea could also be used as a reference. Though dynamic current imbalance could be suppressed by enhancing the consistency of paralleled IGBTs’ gate voltage [9], a better current sharing may not be achieved if the difference in gate circuits is ignored. By analyzing the voltage-current relationship in the switching processes of IGBTs, dynamic current sharing of paralleled IGBTs could be improved by properly adjusting the drive voltage or the delay of its control signal [10]–[15].
The algorithm for obtaining gate delay compensation is proposed with the analysis of the stages that have a great impact on IGBTs’ dynamic current sharing during the turn-on and turn-off processes. The “average delay” and the “absolute delay” gate asynchronous drive methods are presented, dynamic current sharing under these two asynchronous driving modes is analyzed and compared.
Asynchronous Drive and the Analysis of the Key Dynamic Phases
A. Principle of Asynchronous Drive Method
Recent publications show that the compensation of delay time
The method implemented in this work is based on the indirect determination of
B. Analysis of the Key Phases in Dynamic Current Sharing
The turn-on and turn-off processes of IGBT are analyzed under the inductive load of Buck circuit. The driving circuit and power loop of four parallel IGBTs at the switching time are shown in Fig. 2. Four IGBTs share the same driving voltage
1) Key Phases of the Turn-On Process
The turn-on delay phase: Before the turn-on signal arrives, IGBT is in the off-state where the gate voltage \begin{align*} V_{\text {G,on}}=&v_{\text {GE}} + R_{\text {G}} C_{\text {ies}} \frac {\text {d}v_{\text {GE}} }{\text {d}t}\tag{1}\\ i_{\text {C}}=&0\tag{2}\end{align*}
By solving the RC full-response equation, \begin{equation*} v_{\text {GE}} (t)\,\,= V_{\text {G,off}} + (V_{\text {G,on}} - V_{\text {G,off}})\left({1 - e^{ - \frac {t}{C_{\text {ies}} R_{\text {G}}}}}\right)\tag{3}\end{equation*}
Turn-on delay time \begin{equation*} t_{\text {d(on)}} = - C_{\text {ies}} R_{\text {G}} \cdot \ln \frac {V_{\text {G,on}} - V_{\text {GE(th)}} }{V_{\text {G,on}} - V_{\text {G,off}}}\tag{4}\end{equation*}
The collector current rising phase: Collector current tends to increase when gate voltage reaches threshold voltage \begin{align*} V_{\text {G,on}}=&v_{\text {GE}} + R_{\text {G}} C_{\text {ies}} \frac {\text {d}v_{\text {GE}} }{\text {d}t} + L_{\text {Ei}} \frac {\text {d}i_{C} }{\text {d}t}\tag{5}\\ i_{\text {C}}=&\frac {K}{2}(v_{\text {GE}} - V_{\text {GE(th)}})^{2}\tag{6}\end{align*}
It could be obtained by (5) \begin{equation*} L_{\text {Ei}} \cdot \text {d}i_{\text {C}} = V_{\text {G,on}} \text {d}t - R_{\text {G}} C_{\text {ies}} \text {d}v_{\text {GE}} - v_{\text {GE}} \text {d}t\tag{7}\end{equation*}
Approximation is executed after both ends of (7) are integrated \begin{equation*} \Delta i_{\text {C}} = \frac {1}{L_{\text {Ei}} }[V_{\text {G,on}} \Delta t - R_{\text {G}} C_{\text {ies}} \Delta V_{\text {GE}} - V_{\text {GE(ave)}} \Delta t]\tag{8}\end{equation*}
\begin{align*} \begin{cases} \displaystyle \Delta V_{\text {GE}} = V_{\text {GE(pl)}} - V_{\text {GE(th)}} \\ \displaystyle V_{\text {GE(ave)}} = 0.5 \cdot (V_{\text {GE(pl)}} + V_{\text {GE(th)}}) \end{cases}\tag{9}\end{align*}
The variation of collector current during gate voltage rise from
The collector current from one IGBT in parallel with others could be marked as \begin{equation*} V_{\text {GE(pl)}i} = \sqrt {\frac {2I_{C(on)i} }{K}} + V_{\text {GE}(\text {th})i} \quad (i = 1,2,\ldots n)\tag{10}\end{equation*}
In IGBT parallel application, the time \begin{equation*} t_{d(cr)} = \frac {\frac {1}{n}I_{L} L_{Ei} + R_{\text {G}} C_{\text {ies}} \Delta V_{\text {GE}} }{V_{\text {G,on}} - V_{\text {GE(ave)}} }\tag{11}\end{equation*}
2) Key Phases of the Turn-Off Process
Turn-off delay phase: the input capacitance begins to discharge after the driving voltage drops from \begin{align*} v_{\text {GE}} (t)\,\,=&V_{\text {G,on}} + (V_{\text {G,off}} - V_{\text {G,on}})\left({1 - e^{ - \frac {t}{C_{\text {ies}} R_{\text {G}} }}}\right)\qquad \tag{12}\\ t_{\text {d(off)}}=&- C_{\text {ies}} R_{\text {G}} \cdot \ln \frac {V_{\text {GE(pl)}} - V_{\text {G,off}} }{V_{\text {G,on}} - V_{\text {G,off}} }\tag{13}\end{align*}
Collector-emitter voltage rising phase: After the gate voltage drops to the voltage corresponding to the collector current of the IGBT in the linear area, the collector-emitter voltage starts to rise and the gate voltage is maintained near the Miller plateau \begin{equation*} \frac {\text {d}v_{\text {CE}} }{\text {d}t} = \frac {i_{\text {G}} }{C_{\text {GC}} } = \frac {V_{\text {GE(pl)}} - V_{\text {G,off}} }{R_{\text {G}} C_{\text {GC}} }\tag{14}\end{equation*}
After both ends of (14) are multiplied by “dt”, the deformation can be obtained \begin{equation*} dt = \frac {R_{\text {G}} C_{GC} }{V_{\text {GE(pl)}} - V_{\text {G,off}} }dv_{CE}\tag{15}\end{equation*}
The Miller capacitance \begin{equation*} \Delta t = \frac {R_{\text {G}} }{V_{\text {GE(pl)}} - V_{\text {G,off}} }\int _{V_{CE(sat)} }^{V_{CE(de)} } {C_{GC} dv_{CE} }\tag{16}\end{equation*}
The time \begin{align*} \Delta t\approx&\frac {R_{\text {G}} [C_{\text {GC1}} (V_{1} - V_{\text {CE(sat)}}) + C_{\text {GC2}} (V_{\text {CE(dc)}} - V_{1})] }{V_{\text {GE(pl)}} - V_{\text {G,off}} } \\=&t_{\text {d(vr)}}\tag{17}\end{align*}
Implementation of the Asynchronous Drive Method
A. Calculation of Delay Compensation
The delay time for the compensation of dynamic current sharing in paralleled IGBTs could be calculated by using the time information deduced from chapter II. The compensation delay is shown by taking two parallel IGBTs as an example.\begin{align*} \Delta t_{\text {d(on)}}=&\left |{ {t_{\text {d(on)2}} - t_{\text {d(on)1}} } }\right |\tag{18}\\ \Delta t_{\text {d(cr)}}=&\left |{ {t_{\text {d(cr)2}} - t_{\text {d(cr)1}} } }\right |\tag{19}\\ \Delta t_{\text {d(off)}}=&\left |{ {t_{\text {d(off)2}} - t_{\text {d(off)1}} } }\right |\tag{20}\\ \Delta t_{\text {d(vr)}}=&\left |{ {t_{\text {d(vr)2}} - t_{\text {d(vr)1}} } }\right |\tag{21}\end{align*}
B. Determinations of the Delay Times $t_{d}$
1) Determination Based on Parameters Extraction
The calculation of delay times
Extraction of threshold voltage
The extraction of the parameter \begin{equation*} K = \frac {2I_{C} }{\left ({{v_{GE} - V_{GE(th)} } }\right)^{2}}\tag{22}\end{equation*}
2) Determination Based on Indirect Measurements
Since delay times
This work is implemented with the former way to determine delay time in key phases while the latter which needs to guarantee the appropriate thresholds of each electrical parameter measured is not investigated
C. Selection About the Reference Signal
At least one of the paralleled IGBT gate control signals needs to be selected as the reference signal to calculate the compensation delay required for the control signals from the remaining IGBTs. There are two ways to choose the reference signal considering that they may have different influence on dynamic current sharing.
Average delay gate asynchronous drive: select the control signal of the IGBT whose current is closest to the average current as a reference signal and introduce delay in other devices for control.
Absolute delay gate asynchronous drive: select the control signal of the IGBT whose current is the smallest or largest as a reference signal and introduce delay in other devices for control.
In conjunction with the above description, the structure of the asynchronous drive could be summarized in five stages shown in Fig. 3.
Current Sharing Characteristics Simulation of Asynchronous Drive
Double pulse simulation circuit is built as Fig. 4 shows where Z2 is IGBT CM400HA-34H from PSpice library. Z1, Z3 and Z4 are IGBT models generated by CM400HA-34H to cause dynamic current imbalance with the change of the relevant parameters of gate. The load current is set to 1200A by adjusting the width of the first pulse. Some simulation parameter settings are shown in Table 1.
The transfer characteristic curve of CM400HA-34H could be obtained by building test circuit. As a calculation result,
“Parameter value” in Table 2 represents the difference between the set values from Z1, Z3 as well as Z4 and that from Z2. “Turn-on/off key phases delay” in Table 2 corresponds to the time where the paralleled IGBTs accomplish the key phase in the transient process. The compensation delay from Table 3 and Table 4 corresponding to average and absolute delay is calculated by the current distribution (Fig. 5, Fig. 6, Fig. 11 and Fig. 12) and the data from Table 2. The distribution of collector current before and after compensation obtained by simulation is shown in Figs. 516 where Fig. 5, Fig. 6, Fig. 11 and Fig. 12 correspond to the current sharing without compensation, and Fig. 7, Fig. 8, Fig. 13 and Fig. 14 correspond to the current distribution under average delay gate asynchronous drive. The current distribution in Fig. 9, Fig 10, Fig. 15 and Fig. 16 correspond to absolute delay gate asynchronous drive.
Turn-off current distribution with different
Turn-on current distribution with different
Turn-off current distribution with different
Turn-on current distribution with different
Turn-off current distribution with different
Turn-on current distribution with different
Turn-off current distribution with different
Turn-on current distribution with different
Turn-off current distribution with different
Turn-on current distribution with different
Turn-off current distribution with different
Turn-on current distribution with different
Affected by different setting of threshold voltage
The paralleled IGBT with larger gate capacitance (Z4) would spend more time in all key phases of turn-on and turn-off transients. It corresponds well to the current sharing in Fig. 11 and Fig. 12 and the delay time calculated in Table 2.
The control signal of Z3 is regarded as the reference signal for average delay gate asynchronous drive with different threshold voltage
After the selection of the reference signal and the calculation about delay compensation under average/absolute asynchronous drive, the consistency of collector current rising comes to a high level and the difference of collector current both decreases under two types of asynchronous drive (Fig. 7 to Fig. 10). In Fig. 13 and Fig. 15, it could be observed that an improvement of collector current rising consistency occurs under average/absolute asynchronous drive compared with the uncompensated situation. The imbalance of current sharing is smaller in Fig. 14 and Fig. 16 than that of the uncompensated.
The current imbalance [22]–[26] \begin{align*} \delta=&\frac {I_{\text {Cmax}} - I_{\text {Cmin}} }{I_{\text {Ctot}} }\tag{23}\\ \Delta \delta=&\frac {\delta - {\delta }'}{\delta }\tag{24}\end{align*}
Dynamic current sharing is improved by average and absolute delay gate asynchronous drive under two different types of drive circuit parameter settings shown in Table 5 and Table 6 (all imbalance improvement factors
The current imbalance
In the view of the fact that average delay and absolute delay gate asynchronous drive almost obtain the same suppression effect on dynamic current imbalance the extra simulation with different settings of
Distribution of
Distribution of
Distribution of
Distribution of
In Fig. 17, though the imbalance improvement factor
Compared with the distribution of imbalance improvement factor
Experimental Validations of the Asynchronous Drive Method
It is necessary to verify the asynchronous drive method by carrying out experiment. Since output characteristics of drivers should be consistent before IGBT paralleling test, adjustment of delay time needs to be completed. Then, the parameters of gate circuits of each IGBT module are extracted to calculate delay compensation for asynchronous drive. Furthermore, gate voltage and collector current distribution before and after the compensation is established.
A. Adjustment of Drivers and Parameters Extraction of Gate Circuits
The output characteristics of drivers about four IGBT modules are observed without driving IGBT gate circuits. In Fig. 21 and Fig. 22, the output voltage of drivers during turn-on and turn-off processes is presented. It could be found that the output voltage of driver 2 (Channel 2) lags behind others (Channel 1: driver 1, Channel 3: driver 3, Channel 4: driver 4) in turn-off process clearly. In addition, the output voltage of driver 3 and driver 4 also lag behind driver 1 approximately 30ns.
Output characteristics of drivers in turn-off process (Channel 1: driver 1, Channel 2: driver 2, Channel 3: driver 3, Channel 4: driver 4).
Output characteristics of drivers in turn-on process (Channel 1: driver 1, Channel 2: driver 2, Channel 3: driver 3, Channel 4: driver 4).
By introducing delay time to driver 1, driver 3 and driver 4, the consistency of four drivers is ensured. Then, gate voltage distribution of IGBT modules after adjustment is shown in Fig. 23 and 24.
Gate voltage distribution of IGBT modules in turn-off process (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).
Gate voltage distribution of IGBT modules in turn-on process (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).
The parameters of gate circuit is extracted respectively by low power, high power test and consulting data sheet. The basic data of the test bench are summarized in Table 7. The data of gate circuit parameters which will be used in calculation of delay time for compensation are listed in Table 8.
In Table 8, parameter
B. Calculation of Delay Compensation and Double Pulse Test With Four Parallel Connected IGBTS
Associated with the equations in section II, the parameters of gate circuit from four IGBT modules could be turned into the time information. In Table 9, the time information of key phases of the turn-on and turn-off transients is listed to calculate delay compensation shown in Table 10. In view of practicability, absolute delay gate asynchronous drive is used in the experiment. Gate control signal of the module which turn on/off slowly is selected as the reference signal.
Gate control signals of module 2 and module 4 are respectively selected as the reference signals of turn-on process and turn-off process. In consideration of the clock period of CPLD from driver (
Fig. 25 shows a buck converter with six paralleled IGBT half-bridge modules 2MBI200U4H-120 within 200V 400A. In this research, the number of modules is limited to four. The driving signal distribution of paralleled IGBT modules without compensation is shown in Fig. 26, and Fig. 27 shows the driving signal distribution of paralleled IGBT modules with compensation.
The driving signal distribution of IGBT modules, without compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).
The driving signal distribution of IGBT modules, with compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).
In the turn-off process before compensation, the distribution of gate voltage and Collector current about four paralleled IGBT modules are shown in Fig. 28 to Fig. 29.
Gate voltage distribution of IGBT modules in turn-off process, without compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).
Collector current distribution of IGBT modules in turn-off process, without compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).
After compensation, the distribution of gate voltage and Collector current about four paralleled IGBT modules are shown in Fig. 30 to Fig. 31. Although
Gate voltage distribution of IGBT modules in turn-off process, with compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).
Collector current distribution of IGBT modules in turn-off process, with compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).
In the turn-on process before compensation, the distribution of gate voltage and Collector current about four paralleled IGBT modules are shown in Fig. 32 to Fig. 33.
Gate voltage distribution of IGBT modules in turn-on process, without compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).
Collector current distribution of IGBT modules in turn-on process, without compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).
Compared with the collector current distribution without compensation (Fig. 33) in the turn-on transient, the collector current consistency of four paralleled IGBT modules is improved (Fig. 35) as expected. After introducing different delays respectively in the gate control signals of module 1, 3 and 4 (Fig. 34), the moment when their collector currents begin to change and the slopes of their collector current are closer to those of module 2.
Gate voltage distribution of IGBT modules in turn-on process, with compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).
Collector current distribution of IGBT modules in turn-on process, with compensation (Channel 1: module 1, Channel 2: module 2, Channel 3: module 3, Channel 4: module 4).
According to (23) and (24), the current imbalance
Contrasted with the simulation results, though the current imbalance in the turn-on transient is suppressed by asynchronous drive method (
Conclusion
Based on the analysis of the key phases in the turn-on and turn-off processes, average/absolute delay gate asynchronous drive is proposed through the choice of the reference signal. The PSpice simulation of Buck circuit with four paralleled IGBTs is built to cause dynamic current imbalance by setting two types of difference in gate circuit. Then, the comparison of the current imbalance
After the adjustment of drivers’ consistency and extraction of gate circuit parameters, the calculation of compensation delay is achieved. A four paralleled IGBT half-bridge modules experimental setup is established to verify asynchronous driver method, the experimental results show an improvement in dynamic current sharing in the turn-on transient. The unexpected unbalanced current appeared in the turn-off transient is noteworthy to weigh the asymmetry of power loop design and asynchronous gate signal driving method The paralleling of IGBT modules is always applied in high-voltage and large-power occasion where the switching frequency of single IGBT module could hardly exceed 10kHz, and the switching frequency of power devices is far below 1kHz in the application of high voltage great power frequency converters, traction converters for rail transit, wind power converters, HVDC substation, etc. The moments where asynchronous gate signal driving method acts on the paralleled IGBT modules are turn-on process and turn-off process. The time of turn-on process and turn-on process is relatively short compared to the time of on-state regardless of how high the switching frequency of IGBT module is (see in Fig. 3 in this response). So the presented method could complete the compensation task under the switching frequency where all IGBT modules operate normally. The practical compensation delay for paralleled IGBT modules is set under the certain operating conditions by adjusting the delay of driving signal, and the driving circuits would introduce the compensation into each paralleled branch. Under the normal switching frequency for paralleled IGBT modules, the real-time calculation of compensation delay is not necessary for the control system, in other words, there is no strict requirements for operation speed of control system to complete compensation.