Abstract:
The formal verification of integer multipliers is one of the important but challenging problems in the verification community. Recently, the methods based on symbolic com...Show MoreMetadata
Abstract:
The formal verification of integer multipliers is one of the important but challenging problems in the verification community. Recently, the methods based on symbolic computer algebra (SCA) have shown very good results in comparison to all other existing proof techniques. However, when it comes to verification of huge and structurally complex multipliers, they completely fail as an explosion happens in the number of monomials. The reason for this explosion is the generation of redundant monomials known as vanishing monomials. This article introduces the SCA-based approach RevSCA-2.0 that combines reverse engineering and local vanishing removal to verify large and nontrivial multipliers. For our approach, we first come up with a theory for the origin of vanishing monomials, i.e., we prove that the gates/nodes where both outputs of half adders (HAs) converge are the origins of vanishing monomials. Then, we propose a dedicated reverse engineering technique to identify atomic blocks including HAs. The identified HAs are the basis for detecting converging cones and locally removing vanishing monomials, which finally results in a vanishing-free global backward rewriting. The efficiency of RevSCA-2.0 is demonstrated using an extensive set of multipliers with up to several million gates.
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ( Volume: 41, Issue: 5, May 2022)
Funding Agency:
Institute of Computer Science, University of Bremen, Bremen, Germany
Alireza Mahzoon (Graduate Student Member, IEEE) received the master’s degree in electrical engineering from the University of Tehran, Tehran, Iran, in 2016. He is currently pursuing the Ph.D. degree with the Research Group of Computer Architecture, University of Bremen, Bremen, Germany.
He published several papers on international conferences, such as DATE, ICCAD, and DAC. His current research interests include formal veri...Show More
Alireza Mahzoon (Graduate Student Member, IEEE) received the master’s degree in electrical engineering from the University of Tehran, Tehran, Iran, in 2016. He is currently pursuing the Ph.D. degree with the Research Group of Computer Architecture, University of Bremen, Bremen, Germany.
He published several papers on international conferences, such as DATE, ICCAD, and DAC. His current research interests include formal veri...View more
Institute for Complex Systems, Johannes Kepler University Linz, Linz, Austria
Daniel Große (Senior Member, IEEE) received the Dr.-Ing. degree in computer science from the University of Bremen, Bremen, Germany, in 2008.
He remained as a Postdoctoral Researcher with the Group of Computer Architecture, University of Bremen, Bremen, Germany. In 2010, he was a substitute Professor of Computer Architecture with Albert-Ludwigs University, Freiburg im Breisgau, Germany. From 2013 to 2014, he was the CEO of ...Show More
Daniel Große (Senior Member, IEEE) received the Dr.-Ing. degree in computer science from the University of Bremen, Bremen, Germany, in 2008.
He remained as a Postdoctoral Researcher with the Group of Computer Architecture, University of Bremen, Bremen, Germany. In 2010, he was a substitute Professor of Computer Architecture with Albert-Ludwigs University, Freiburg im Breisgau, Germany. From 2013 to 2014, he was the CEO of ...View more
Institute for Complex Systems, Johannes Kepler University Linz, Linz, Austria
Rolf Drechsler (Fellow, IEEE) received the Diploma and Dr.Phil.nat. degrees in computer science from J. W. Goethe University Frankfurt am Main, Frankfurt, Germany, in 1992 and 1995, respectively.
He was with the Institute of Computer Science, Albert-Ludwigs University, Freiburg im Breisgau, Germany, from 1995 to 2000, and the Corporate Technology Department, Siemens AG, Munich, Germany, from 2000 to 2001. Since 2001, he ha...Show More
Rolf Drechsler (Fellow, IEEE) received the Diploma and Dr.Phil.nat. degrees in computer science from J. W. Goethe University Frankfurt am Main, Frankfurt, Germany, in 1992 and 1995, respectively.
He was with the Institute of Computer Science, Albert-Ludwigs University, Freiburg im Breisgau, Germany, from 1995 to 2000, and the Corporate Technology Department, Siemens AG, Munich, Germany, from 2000 to 2001. Since 2001, he ha...View more
Contents Institute of Computer Science, University of Bremen, Bremen, Germany
Alireza Mahzoon (Graduate Student Member, IEEE) received the master’s degree in electrical engineering from the University of Tehran, Tehran, Iran, in 2016. He is currently pursuing the Ph.D. degree with the Research Group of Computer Architecture, University of Bremen, Bremen, Germany.
He published several papers on international conferences, such as DATE, ICCAD, and DAC. His current research interests include formal verification and debugging of arithmetic circuits with a focus on highly complex and industrial multipliers.
Mr. Mahzoon received the best paper award at ICCAD 2018.
Alireza Mahzoon (Graduate Student Member, IEEE) received the master’s degree in electrical engineering from the University of Tehran, Tehran, Iran, in 2016. He is currently pursuing the Ph.D. degree with the Research Group of Computer Architecture, University of Bremen, Bremen, Germany.
He published several papers on international conferences, such as DATE, ICCAD, and DAC. His current research interests include formal verification and debugging of arithmetic circuits with a focus on highly complex and industrial multipliers.
Mr. Mahzoon received the best paper award at ICCAD 2018.View more
Institute for Complex Systems, Johannes Kepler University Linz, Linz, Austria
Daniel Große (Senior Member, IEEE) received the Dr.-Ing. degree in computer science from the University of Bremen, Bremen, Germany, in 2008.
He remained as a Postdoctoral Researcher with the Group of Computer Architecture, University of Bremen, Bremen, Germany. In 2010, he was a substitute Professor of Computer Architecture with Albert-Ludwigs University, Freiburg im Breisgau, Germany. From 2013 to 2014, he was the CEO of the EDA start-up solvertec focusing on automated debugging techniques. Since 2015, he has been a Senior Researcher with the University of Bremen and the German Research Center for Artificial Intelligence, and the Scientific Coordinator of the Graduate School System Design, funded within the German Excellence Initiative. Since July 2020, he has been a Full Professor with the Johannes Kepler University Linz, Linz, Austria, where he is the Head of the Institute for Complex Systems (ICS). His current research interests include verification, virtual prototyping, debugging, synthesis, and RISC-V. He published over 150 papers in peer-reviewed journals and conferences in the above areas.
Prof. Große received best paper awards (FDL 2007, DVCon Europe 2018, ICCAD 2018, and FDL 2020) as well as business-related awards (IKT Innovativ Award 2013, Weconomy Award 2013, and Embedded Award 2014). He served in program committees of numerous conferences, including ASP-DAC, DAC, DATE, ICCAD, CODES+ISSS, FDL, and MEMOCODE. He is an Allied Member of the Accellera Systems Initiative in the SystemC Verification Working Group.
Daniel Große (Senior Member, IEEE) received the Dr.-Ing. degree in computer science from the University of Bremen, Bremen, Germany, in 2008.
He remained as a Postdoctoral Researcher with the Group of Computer Architecture, University of Bremen, Bremen, Germany. In 2010, he was a substitute Professor of Computer Architecture with Albert-Ludwigs University, Freiburg im Breisgau, Germany. From 2013 to 2014, he was the CEO of the EDA start-up solvertec focusing on automated debugging techniques. Since 2015, he has been a Senior Researcher with the University of Bremen and the German Research Center for Artificial Intelligence, and the Scientific Coordinator of the Graduate School System Design, funded within the German Excellence Initiative. Since July 2020, he has been a Full Professor with the Johannes Kepler University Linz, Linz, Austria, where he is the Head of the Institute for Complex Systems (ICS). His current research interests include verification, virtual prototyping, debugging, synthesis, and RISC-V. He published over 150 papers in peer-reviewed journals and conferences in the above areas.
Prof. Große received best paper awards (FDL 2007, DVCon Europe 2018, ICCAD 2018, and FDL 2020) as well as business-related awards (IKT Innovativ Award 2013, Weconomy Award 2013, and Embedded Award 2014). He served in program committees of numerous conferences, including ASP-DAC, DAC, DATE, ICCAD, CODES+ISSS, FDL, and MEMOCODE. He is an Allied Member of the Accellera Systems Initiative in the SystemC Verification Working Group.View more
Institute for Complex Systems, Johannes Kepler University Linz, Linz, Austria
Rolf Drechsler (Fellow, IEEE) received the Diploma and Dr.Phil.nat. degrees in computer science from J. W. Goethe University Frankfurt am Main, Frankfurt, Germany, in 1992 and 1995, respectively.
He was with the Institute of Computer Science, Albert-Ludwigs University, Freiburg im Breisgau, Germany, from 1995 to 2000, and the Corporate Technology Department, Siemens AG, Munich, Germany, from 2000 to 2001. Since 2001, he has been with the University of Bremen, Bremen, Germany, where he is currently a Full Professor and the Head of the Group for Computer Architecture, Institute of Computer Science. In 2011, he became the Director of the Cyber-Physical Systems Group, German Research Center for Artificial Intelligence, Bremen, Germany. His current research interests include the development and design of data structures and algorithms with a focus on circuit and system design.
Prof. Drechsler was a recipient of best paper awards at HVC in 2006, FDL in 2007, 2010, and 2020, DDECS in 2010, DSD in 2020, and ICCAD in 2013 and 2018. He was a member of Program Committees of numerous conferences, including DAC, ICCAD, DATE, ASP-DAC, FDL, MEMOCODE, and FMCAD, the Symposium Chair of ISMVL 1999 and 2014 and ETS 2018, and the Topic Chair for “Formal Verification” at DATE 2004, DATE 2005, DAC 2010, and DAC 2011 and 2018. He was the General Chair of the ETS 2018 and the Program Chair of ICCAD 2020. He is an Associate Editor of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and IEEE Transactions on Very Large Scale Integration, and further journals.
Rolf Drechsler (Fellow, IEEE) received the Diploma and Dr.Phil.nat. degrees in computer science from J. W. Goethe University Frankfurt am Main, Frankfurt, Germany, in 1992 and 1995, respectively.
He was with the Institute of Computer Science, Albert-Ludwigs University, Freiburg im Breisgau, Germany, from 1995 to 2000, and the Corporate Technology Department, Siemens AG, Munich, Germany, from 2000 to 2001. Since 2001, he has been with the University of Bremen, Bremen, Germany, where he is currently a Full Professor and the Head of the Group for Computer Architecture, Institute of Computer Science. In 2011, he became the Director of the Cyber-Physical Systems Group, German Research Center for Artificial Intelligence, Bremen, Germany. His current research interests include the development and design of data structures and algorithms with a focus on circuit and system design.
Prof. Drechsler was a recipient of best paper awards at HVC in 2006, FDL in 2007, 2010, and 2020, DDECS in 2010, DSD in 2020, and ICCAD in 2013 and 2018. He was a member of Program Committees of numerous conferences, including DAC, ICCAD, DATE, ASP-DAC, FDL, MEMOCODE, and FMCAD, the Symposium Chair of ISMVL 1999 and 2014 and ETS 2018, and the Topic Chair for “Formal Verification” at DATE 2004, DATE 2005, DAC 2010, and DAC 2011 and 2018. He was the General Chair of the ETS 2018 and the Program Chair of ICCAD 2020. He is an Associate Editor of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and IEEE Transactions on Very Large Scale Integration, and further journals.View more
