A 53GΩ@DC Input Impedance Multi-Channel Neural Recording Amplifier with 0.77 μVrms Input-Referred Noise for Deep Brain Implants

Summary form only given. High-quality brain signal acquisition is critically important in brain research for diagnosis and treatment purposes. This calls for a brain interface module to communicate with the brain through micro-scale electrodes. Such a micro-scale electrode system requires an analog front-end (AFE) to amplify the brain signals with the highest quality and accuracy. Recently, fully implantable chronic devices for long-term brain recording have received high attention due to several benefits such as high stability, possibility of recording from a specific population of neurons, and high signal quality. In deep brain recording implants, the interaction between the brain tissue and the electrodes causes a large impedance mismatch at the input of the AFE. This impedance mismatch in some cases can be up to >1 MO [2], thus an important requirement of the AFE for such an application is a high input impedance (over GO range at DC)[3] to tolerate the electrode-tissue impedance mismatch. The performance of input-referred noise (IRN) of the AFE is also an important factor to determine the smallest signal that the AFE can capture. The bandwidth of the AFE is determined based on the application to capture local field potential (LFP), action potential (AP), or both. This paper presents a multichannel, high input impedance AFE with low IRN that can amplify both LFP and AP signals. It shows the overall 4-channels architecture of the proposed AFE. To achieve such a high input impedance, single-ended amplifiers are used as a buffer between the input and the second stage, i.e. a Capacitively Coupled Instrumentation Amplifier (CCIA) making use of a chopper-stabilized amplifier. Each reference buffer is shared between two channels, thus, a 4-channel system requires six buffers (4 channel buffers and 2 reference buffers). The buffer consists of a two-stage differential-input single-output amplifier in negative unit feedback with a high open-loop gain of 60dB. The output stage of the reference buffers is optimized to have half the output impedance of the channel buffers. The difference in output impedance allows reducing the common-mode voltage mismatching that occurs at the interface between the buffer and the CCIA stages. The differential input pair of both reference and channel buffers are identical to reduce the input impedance mismatch of the AFE, which affects the overall CMRR. The CCIA stage is chosen as the primary amplifier stage for reducing the offset, achieving low IRN and high CMRR with a gain of 38 dB over the frequency range of 2Hz-2.4kHz. The flicker noise generated by the buffers continues to affect the circuit regardless of the use of the chopper stabilization in the CCIA, thus, the power consumption and size of the input transistor are sacrificed to achieve a low IRN buffer. The total active area of six buffers occupies 20% of the 4-channel AFE area while consuming 40% of its overall power consumption.