A Single Phase, Single Stage AC-DC Multilevel LLC Resonant Converter With Power Factor Correction

Single stage LLC resonant converters with inherent power factor correction are getting popularity in AC-DC converters due to its reduced size and weight. However, single stage topologies are usually less efficient in regulating the dc bus capacitor voltage pertaining to line and load transients. This paper proposes a multi-level flying capacitor based single stage AC-DC LLC topology to address the issue of voltage balancing of dc-bus capacitor and to reduce the voltage stress of the switching devices. The proposed three-level inverter topology guarantees zero voltage switching, less circulating currents, reduced switching stress and losses. The converter uses bridgeless rectification scheme for better efficiency and the power factor is made nearly unity by operating the source-side inductor in discontinuous current conduction. Variable switching frequency control is used to regulate the output voltage of the converter and pulse width modulation is used to control the dc-bus voltage. This dual control scheme is very effective to keep the dc-bus voltage nearly constant over a wide range of line and load variations. The proposed topology and control scheme have been validated by hardware results on a 250W resistive load.

SECTION I. Introduction

Soft switching of switching devices, inherent short circuit and open circuit protection, and high efficiency are some of the benefits of LLC resonant converters [2]–​[4]. They can work at very high switching frequency which reduces the size and weight of the converter and are well suited for applications like electric vehicle battery charging. However, in AC-DC applications, a front end boost power factor correction (PFC) stage is usually needed to improve the power factor [3]. The recent trend is to use a single power converter for controlling both the power factor stage and LLC stage (see Fig. 1) where the operation of the input inductor in the discontinuous conduction mode helps to shape the average input current without any closed loop control thereby improving the power factor [5], [6]. However, the average output power of the converter may not be equal to that of the PFC stage during load variations and transients. This power imbalance causes the DC bus capacitor voltage to vary until energy balance is achieved [5]. These variations can lead to unstable operation of the converter or even to the destruction of bus capacitor due to over-voltage.

FIGURE 1.

Conventional single-stage LLC converter.

To avoid this issue and to achieve energy balance with a reasonable DC bus voltage, the controller generally shifts the switching frequency of the converter and at low loads, the switching frequency of the converter may reach extreme levels causing high switching losses and control difficulties. In [7]–​[9], a burst mode control scheme is used where the controller pauses the switching action for a certain time intervals based on the bus capacitor voltage and output DC voltage when the switching frequency increases to extreme high levels. This leads to transients in the voltage and current waveforms and the normal functioning of the controller gets disrupted. Furthermore, the burst mode of operation introduces low frequency components in the voltage necessitating extra filtering.

In [10], a modular multilevel based LLC resonant converter has been proposed which is capable of operating the converters over a narrow frequency range for a wide range of input voltage variations with the help of an additional feed forward control by switching in and out of modules. However, the requirement for a large number of switching devices and the charge balancing requirement of the modules limits them for high voltage applications. In [6], a bridgeless topologies for AC/DC resonant converters have been proposed. The converter can return additional energy stored in the DC bus capacitor back to the supply thus regulating the DC bus voltage. However, returning power to the grid distorts the current waveform and increases the total harmonic distortion (THD).

High voltage stress experienced by the switching devices is another drawback of these converters. In [1], [11]–​[18], multilevel inverters are used for reducing the voltage stress across switching devices and to increase the power range of LLC resonant converters. Different types of single stage bridgeless PFC topologies have been presented in literature [19]–​[23]. However, they suffer from shortcomings such as poor DC bus voltage regulation, High switching frequency at light loads, requirement of more switching devices and high voltage stress.

This paper proposes a novel bridgeless topology based on a three-level flying capacitor inverter. The multilevel configuration reduces the voltage stress across switching devices. The bridgeless operation reduces conduction loss. The three-level voltage waveform of the topology gives additional freedom to control the duty ratio of the PFC stage (refer Fig. 3b). The output voltage of the converter is regulated by switching frequency control and the DC bus capacitor voltage is regulated by controlling the duty ratio of switches. But during light loads, duty ratio control is used to regulate the output DC voltage keeping the switching frequency constant. This prevents the converter from extreme high switching frequency during low loads. The topology guarantees zero voltage switching for all the IGBT switches. The converter is operated in discontinuous conduction mode, which is useful in achieving natural power factor correction.

FIGURE 2.

Proposed three-level single stage LLC converter.

FIGURE 3.

Input voltage to the LLC stage $V_{AB}$ .

The paper is organized as follows: Section II discusses the proposed topology and section III presents the different modes of operation. Section IV is about the steady-state analysis. A comparison of the proposed topology with conventional topology is given in section V. Control strategy is discussed in section VI. The experimental results and analysis are presented in Section VII. Finally, part VIII concludes the work.

SECTION II. Proposed Topology

In the proposed topology, a three-level flying capacitor-based inverter constitutes the rectification stage, boost stage as well as the inverter stage (see Fig. 2). The same switches control both the LLC and the boost stages. Here, the converter operates in discontinuous conduction mode, which assures unity displacement power factor. The voltage applied to the LLC stage contains three discrete levels (see Fig. 3b) unlike the two level waveform in conventional single-stage converters (See Fig. 3a) [5]. This three-level voltage pattern helps the controller to adjust the duty ratio without disturbing the waveform symmetry and thereby regulating the DC bus voltage. Controlling the DC bus voltage is crucial for the protection of capacitors and for limiting the voltage stress of the switching devices for a wide range of load and input variations. In the proposed topology, zero voltage switching (ZVS) of the IGBT switches is naturally achieved by incorporating LLC based resonant stage. A full-wave Schottky rectifier with a filter capacitor comprises the output side of the converter. In order to get voltage symmetry across the LLC terminal, the voltage across capacitors $C_{1}$ , $C_{2}$ , and $C_{3}$ should be at the same voltage level $(V_{DC}/2)$ . The switch pairs $Q_{1}$ , $\overline {Q_{1}}$ and $Q_{2}$ , $\overline {Q_{2}}$ operates in a complementary fashion. The working of LLC resonant converter is similar to that of conventional converters and is not repeated here [24], [25]. This paper focuses on the issue of capacitor balancing and the modes of operation are outlined in the next section.

SECTION III. Modes of Operation

The eight different operational modes of the proposed converter are presented in Fig. 4. Modes 1 to 4 describe operation for positive half cycle of the input AC supply whereas modes 5 to 8 are related to negative half cycle of the input AC supply.

• Mode 1 (See Fig. 4a):

  Switches $Q_{1}$ and $Q_{2}$ are turned ON. The current in the input inductor $L_{in}$ increases and energy is stored in the inductor. The voltage across LLC terminals is the voltage across capacitor $C_{3}$ ($V_{AB}=-V_{DC}/2$ ).

• Mode 2:

  Switch $Q_{2}$ is turned OFF. Inductor current decays through $C_{1}$ and $\overline {D_{2}}$ . The voltage across $\overline {Q_{2}}$ now falls to zero making it ready to turn ON at ZVS. $\overline {Q_{2}}$ is then turned ON. In this mode, the input inductor current discharges $C_{1}$ and charges capacitors $C_{2}$ and $C_{3}$ . The voltage across LLC is zero ($V_{AB}=0$ ) in this mode. Fig. 4b represents this mode of operation.

• Mode 3:

  Switch $Q_{1}$ is turned OFF. Current completes its path through $\overline {D_{1}}$ . Voltage across the switch $\overline {Q_{1}}$ drops to zero. $\overline {Q_{1}}$ is then turned ON at ZVS. Input inductor charges capacitors $C_{2}$ and $C_{3}$ . The voltage across LLC is equal to the voltage across capacitor $C_{2}$ ($V_{AB}= +V_{DC}/2$ ). Fig. 4c shows the mode.

• Mode 4:

  In this mode, the switch $\overline {Q_{2}}$ is turned OFF. The current flowing through the LLC turns ON the diode $D_{2}$ making the switch $Q_{2}$ ready to be turned ON at ZVS. The switch $Q_{2}$ is then turned ON. Capacitor $C_{1}$ gets charged up. The voltage across the LLC terminals falls to zero ($V_{AB}= 0$ ). Fig. 4d depicts the mode. At the end of this mode, input inductor completely discharges but the lagging current flowing through the LLC circuit turns ON the diode $D_{1}$ and $D_{2}$ . Now the switches $Q_{1}$ and $Q_{2}$ are ready to be turned ON at ZVS (mode 1).

FIGURE 4.

Different operating modes of the converter. Modes (1–​4) and (5–​8) represents the different modes during the positive and negative half cycles of the input supply $V_{AC}$ .

The working modes 5 to 8 during the negative half cycle of the input supply (see Fig. 4) are similar to the modes 1 to 4 of the positive half cycle and is not explained here.

Fig. 5 shows the timing diagram of gate pulses, input inductor current, and LLC voltage ($V_{AB}$ ) for different modes of operation. It also explains how to balance the flying capacitor voltage $V_{C1}$ . Mode 4 charges $C_{1}$ and mode 2 discharges it. Hence if $V_{C1}$ is less than $V_{DC}/2$ then mode 2 will not be used in that cycle of the converter (refer Fig. 5a). Similarly, to decrease $V_{C1}$ , mode 4 is withdrawn and mode 2 is inserted in that cycle of converter (see Fig. 5b). So in any cycle of the converter (during positive cycle of input supply) either mode 2 or mode 4 is used to balance $V_{C1}$ . During the negative half cycle of the input supply, mode 6 and mode 8 are used to charge and discharge $C_{1}$ respectively.

FIGURE 5.

Timing diagram based on different modes of operation.

SECTION IV. Steady State Analysis

In this section, the relationship between DC bus voltage, power, frequency and duty ratio for the boost stage and LLC stages of the converter are analyzed with mathematical equations and plots. The steady-state equations for the LLC stage are derived based on the first-order approximation (FHA) technique [26]. The accuracy of the first order approximation method is greatest when the frequency of the input square wave is near to the series resonant frequency.

A. Boost Stage

In discontinuous conduction mode the input inductor current starts and ends at zero in each switching cycle. Input inductor, $L_{in}$ stores energy during mode 1 (refer Fig. 4) and the peak value of inductor current at the end of mode 1 is given by (refer Fig. 6):

$$\begin{align*} v_{AC}=&L_{in}\frac {di_{Lin}}{dt}; (0 \leq t \leq DT_{s}) \tag{1}\\ I_{Lin\_{}peak}=&\frac {v_{AC}DT_{s}}{L_{in}}; (t = DT_{s})\tag{2}\end{align*}$$ where

• $i_{Lin}$ is the current through input inductor;

• $I_{Lin\_{}peak}$ is the maximum value of $i_{Lin}$ ;

• ‘D’ is the duty ratio;

• $v_{AC}$ is the instantaneous value of input ac voltage;

• $T_{s}$ is the switching frequency.

FIGURE 6.

Input current and voltage in discontinuous conduction mode.

Mode 1 is followed by mode 2 or by mode 4 where, input inductor current $i_{Lin}$ decays to a lower value (refer Fig. 4). The expression for $i_{Lin}$ during this mode assuming $i_{Lin}>0$ through out this mode is given by (refer Fig. 6):

$$\begin{align*} v_{AC}-\frac {V_{DC}}{2}=&L_{in}\frac {di_{Lin}}{dt}; \left({DT_{s} \leq t \leq \frac {T_{s}}{2}}\right) \tag{3}\\ i_{Lin}=&\frac {(2v_{AC}-V_{DC})(1-2D)T_{s}}{4L_{in}}\!+\!I_{Lin\_{}peak};~ t\!=\!\frac {T_{s}}{2} \\\tag{4}\end{align*}$$

By substituting the value of $I_{Lin\_{}peak}$ from (2) in (4), the condition for which $i_{Lin}$ greater than zero within mode 2 can be determined as shown below:

$$\begin{align*} i_{Lin}=&\frac {(2v_{AC}-V_{DC})(1-2D)T_{s}}{4L_{in}}+\frac {v_{AC}DT_{s}}{L_{in}}\geq 0;\quad t=\frac {T_{s}}{2} \\ \tag{5}\\ v_{AC}>&\frac {(1-2D)V_{DC}}{2}\tag{6}\end{align*}$$

If the condition given in (6) is not satisfied, then the input current $i_{Lin}$ reaches zero before the end of mode 2. Let $d_{1}T_{s}$ be the time taken for $i_{Lin}$ to reach zero before the end of mode 2. The expression for $I_{Lin\_{}peak}$ can be calculated from the decay slope of mode 2 and is given by:

$$\begin{equation*} I_{Lin\_{}peak}=\frac {\left({\frac {V_{DC}}{2}-v_{AC}}\right)d_{1}T_{s}}{L_{in}}\tag{7}\end{equation*}$$ By equating (2) and (7), $d_{1}$ can be expressed as: $$\begin{equation*} d_{1}=\frac {D v_{AC}}{\frac {V_{DC}}{2}-v_{AC}}\tag{8}\end{equation*}$$

If the input inductor current $i_{Lin}$ has not decayed to zero completely in mode 2, the value of $i_{Lin}$ at the beginning of mode 3 can be obtained from the decay slope of $i_{Lin}$ (refer Fig. 6):

$$\begin{align*} v_{AC}-V_{DC}=&L_{in}\frac {di_{Lin}}{dt};\hspace {0.6cm} \left({\frac {T_{s}}{2} \leq t \leq \left({\frac {T_{s}}{2}+d_{2}T_{s}}\right)}\right) \tag{9}\\ i_{Lin}=&\frac {(V_{DC}-v_{AC})d_{2}T_{s}}{L_{in}};\left({t=\frac {T_{s}}{2}}\right)\tag{10}\end{align*}$$ where $d_{2}T_{s}$ is the time required for the inductor current to reach zero. By equating (4) and (10) an expression for $d_{2}$ can be derived as given below: $$\begin{equation*} d_{2}=\frac {2v_{AC}+V_{DC}(2D-1)}{4(V_{DC}-v_{AC})}\tag{11}\end{equation*}$$

The converter should be able to ensure discontinuous conduction mode under all operating conditions. The maximum value of input inductance to guarantee discontinuous conduction mode can be derived by applying the boundary conditions when the converter is operated at 50% duty ratio and when the input supply voltage at its maximum $V_{m}$ (refer Fig. 7). The average value of input inductor current $I_{Lm}$ for this switching cycle is given by:

$$\begin{equation*} I_{Lm}=\frac {I_{Lm\;peak}}{2}=\frac {V_{m}DT_{s}}{2L_{in}}\tag{12}\end{equation*}$$ where, $I_{Lm\;peak}$ is the peak value of inductor current for the maximum input supply voltage $V_{m}$ . At the boundary between continuous and disconduction modes, the output voltage of the converter is given by: $$\begin{equation*} V_{m}=(1-D)V_{DC}\tag{13}\end{equation*}$$

FIGURE 7.

Boost stage converter at the boundary of Continuous – discontinuous mode.

Substituting (13) into (12) gives the maximum value of input inductance.

$$\begin{equation*} L_{in} \leq \frac {V_{DC}D(1-D)T_{s}}{2I_{Lm}}\tag{14}\end{equation*}$$

The average input inductor current over one switching cycle is given by:

$$\begin{align*}&\hspace {-.5pc}i_{Lin\_{}avg}=\frac {1}{T_{s}}\left ({\int _{0}^{DT_{s}}i_{Lin}dt}\right. +\int _{DT_{s}}^{\frac {T_{s}}{2}}i_{Lin}dt \\&\qquad\qquad\qquad\qquad\qquad\qquad\left.{+\int _{\frac {T_{s}}{2}}^{\frac {T_{s}}{2}+d_{2}T_{s}}i_{Lin}dt}\right)\tag{15}\end{align*}$$

The average input power of the converter can be found by substituting the value of average input current from (15) into the following equation:

$$\begin{equation*} P_{in\_{}avg}=\int _{0}^{T_{s}}(i_{Lin\_{}avg}\times v_{AC})dt\tag{16}\end{equation*}$$

The equation (16) is simulated and the effect of duty ratio on the input power is plotted in Fig. 8. The variation of duty ratio is almost proportional to the input power of the converter. Therefore regulating duty ratio provides a good control over the input power of the converter. The input power is inversely proportional to the normalized switching frequency of the converter (see Fig. 9). At high switching frequencies, the variation in input power is small. Fig. 10 shows the variation in DC bus voltage with input power due to load variation without having frequency or duty ratio control. The high DC bus voltage at lower input power can even lead to the destruction of the capacitor which necessitates the importance of regulating the DC bus voltage.

FIGURE 8.

Input power of the boost stage converter vs. duty ratio, $f_{sw}$ = 18kHz, $V_{DC}$ = 750V.

FIGURE 9.

Input power of the boost stage converter vs. frequency, $f_{r}$ = 15kHz, $V_{DC}$ = 750V, D = 0.35.

FIGURE 10.

Input power of the boost stage converter vs. DC bus voltage, $f_{sw}$ = 18kHz, D = 0.35.

B. LLC Stage

The equivalent representation of LLC converter referred to primary is shown in Fig. 11. The input voltage to the primary circuit is assumed to be a stepped square wave having peak voltage $\pm \frac {V_{DC}}{2}$ . The fundamental component of input voltage to LLC stage is given by

$$\begin{equation*} v_{in}^{F} = \frac {8V_{DC}sin\left({\frac {D}{2}}\right)}{2\pi }sin\:\omega t\tag{17}\end{equation*}$$

FIGURE 11.

Equivalent representation of LLC referred to the primary side.

On the output side (refer Fig. 11 & Fig. 12), the fundamental component of voltage $nv_{RI}^{F}$ is given by:

$$\begin{equation*} nv_{RI}^{F} = \frac {4nV_{o}}{\pi }sin\:\omega t\tag{18}\end{equation*}$$ where ‘n’ is the turns ratio.

FIGURE 12.

Equivalent representation of the secondary side of the transformer.

The voltage gain of LLC stage (M) can be found from the equivalent circuit representation shown in Fig. 11.

$$\begin{align*} M = \frac {n\:v_{RI}^{F}}{v_{in}^{F}}=&\frac {\frac {4nV_{o}}{\pi }sin\:\omega t}{\frac {8V_{DC}sin\left({\frac {D}{2}}\right)}{2\pi }sin\:\omega t} = \frac {nV_{o}}{sin\left({\frac {D}{2}}\right)V_{DC}} \tag{19}\\ M=&\left |{ \frac {\left({\frac {\omega }{\omega _{o}}}\right)^{2}A}{{\left[{\frac {\omega }{\omega _{o}}^{2}(A+1)-1}\right]+j\left({\frac {\omega }{\omega _{o}}^{2}-1}\right)\frac {\omega }{\omega _{o}}AQ}}}\right |\tag{20}\end{align*}$$ where A is the ratio of magnetizing inductance $L_{m}$ to resonant inductance $L_{r}$ ; $f_{o}$ is the resonant frequency which is given by: $$\begin{equation*} f_{o}=\frac {1}{2 \pi \sqrt {L_{r}C_{r}}}\tag{21}\end{equation*}$$

Q is the quality factor which is given by:

$$\begin{align*} Q=&\frac {\sqrt {L_{r}/C_{r}}}{R_{ac\_{}p}} \tag{22}\\ R_{ac\_{}p}=&\frac {8n^{2}R_{o}}{\pi ^{2}}\tag{23}\end{align*}$$ where $R_{ac\_{}p}$ is AC equivalent of load resistance referred to primary. $R_{o}$ is the output load resistance.

From (20) it is obvious that the voltage gain of the LLC stage depends on Q, $f_{sw}$ and A. Fig. 13 shows possible variations of voltage gain for different values of Q (0.2-10) and ($\frac {L_{m}}{L_{r}}$ ). Based on the required frequency range of operation and desired voltage gain, Q and A values can be selected from the plot. The desired voltage gain M needed for the converter can be found from the equation (19).

FIGURE 13.

Plots of LLC voltage gain function (M) vs. normalized frequency ($f_{sw}/f_{r}$ ), (a) A=1, (b) A=6.

Since the output load of the converter is known, LLC stage power can be calculated as given below:

$$\begin{equation*} P_{LLC}=\frac {V_{o}^{2}}{R_{o}}\tag{24}\end{equation*}$$

The value of $V_{o}$ can be found by equating (19) & (20). It is then substituted into (24).

$$\begin{align*}&\hspace {-.5pc}P_{LLC}= \frac {sin^{2}\left({\frac {D}{2}}\right)V_{DC}^{2}}{n^{2}R_{o}} \\&\qquad\cdot \left ({\left |{ \frac {\left({\frac {\omega }{\omega _{o}}}\right)^{2}A}{{\left[{\frac {\omega }{\omega _{o}}^{2}(A+1)-1}\right]+j\left({\frac {\omega }{\omega _{o}}^{2}-1}\right)\frac {\omega }{\omega _{o}}AQ}}}\right |}\right)^{2}\tag{25}\end{align*}$$

From (25), it is clear that the power of the LLC stage depends on the duty ratio. Fig. 14a & 14b shows the variation of output power with normalized frequency and duty ratio, respectively. Increasing the ratio $\frac {L_{m}}{L_{r}}$ , make the curve much flatter. However, for a wide range of output power, the converter requires extremely large variation in frequency. Operating the converter at low frequencies away from series resonance increases the circulating current through the LLC and increases the losses [26]. For switching frequencies greater than series resonant frequency, the magnitude of circulating current is small but higher switching frequency increase switching losses. Flow of circulating current is similar to that of conventional LLC converters [26] and therefore it is not explained here. The operation and working of the resonant tank are similar to that in conventional topology. Hence the small signal analysis can found be in [27].

FIGURE 14.

Plots of LLC stage power, (a) Output power $P_{o}$ vs. normalized frequency ($f_{sw}/f_{r}$ ) (Duty ratio constant), (b) Output power $P_{o}$ vs. duty ratio (frequency constant).

C. Input Filter Design

A normal LC filter can be introduced before the converter for filtering the input current (refer Fig. 15). The cut-off frequency $f_{c}$ of the LC filter is taken as 0.7 times the series resonant frequency $f_{r}$ , which is taken as the minimum operating frequency of the converter.

$$\begin{equation*} f_{c} = \frac {1}{2\:\pi \:\sqrt {L_{f}C_{f}}}\tag{26}\end{equation*}$$ where $L_{f}$ and $C_{f}$ are filter inductance and capacitance.

FIGURE 15.

LC Filter circuit.

SECTION V. Comparison With Conventional Single Stage AC-DC LLC Resonant Converters

The proposed topology has all advantages of conventional topologies [5]–​[9] such as natural power factor correction, single-stage operation and zero voltage switching. The additional advantages of the proposed topology compared to conventional topologies are as follows. The proposed topology uses 6 switching devices (2 diodes and 4 IGBT) to generate a three-level voltage to the LLC stage with two control parameters (duty ratio and switching frequency). The conventional topologies use the same number of switching devices (4 diodes and 2 IGBT) to generate two-level voltage for the LLC stage with a single control variable (switching frequency). The bridgeless topologies [6] use only 4 switching devices. However, they don’t have the following benefits:

Dual control variables is a major advantage of the proposed topology. The controller can regulate the DC bus voltage and output DC voltage separately by varying duty ratio and switching frequency. In conventional two-level single-stage converters, to maintain the voltage symmetry of the LLC stage, their duty ratio must be fixed at 50%. To ensure discontinuous operation, the inductor current’s decay slope must be greater than the rising slope. For this, the DC bus voltage must be at least two times greater than the maximum input supply voltage $V_{m}$ [5]–​[9]. But for the proposed converter inductor current decaying time can be increased and therefore the DC bus voltage can have lower values. Furthermore, in the proposed topology, due to the multilevel configuration, the voltage stress across the switching devices is half the voltage stress in the conventional topology (refer Fig. 1).

In conventional topologies [5]–​[9], switching frequency is the only control variable. To operate the converter at 33% of the full load, the frequency must be nearly three times the series resonant frequency [5] (refer Fig. 14a). To avoid these extreme high switching frequencies, the conventional system enters into burst mode when the frequency reaches (2-3) times the resonant frequency. However, in the proposed topology, the maximum switching frequency is fixed at 1.5 times the series resonant frequency. Beyond that, duty ratio control is activated to control the output power. This is explained in the next section. By using duty ratio control, the load can be reduced to no load keeping the switching frequency constant at 1.5 times the resonant frequency $f_{r}$ .

SECTION VI. Control Strategy

In contrast with traditional AC-DC LLC based single-stage converters, the proposed topology gives an additional freedom of controlling the duty ratio apart from switching frequency control. The duty ratio of the three-level voltage is varied to vary the energy stored in the inductor. Increasing the duty ratio increases the energy stored by the input inductor. This stored energy ultimately reaches the capacitor during the energy discharge cycle, raising the DC bus voltage.

Fig. 16 shows the control block diagram of the proposed circuit. During regular operation, the duty ratio controller regulates the DC bus voltage by varying the duty ratio. The controller estimates the duty ratio from the error in DC bus voltage. The frequency controller regulates the output DC voltage by varying the switching frequency of the converter. From the error in output voltage, PI generates a control signal. The signal is used together with a counter logic to generate a sawtooth waveform, which has its maximum value equal to the control signal. The sawtooth waveform is then compared with the duty ratio signal from the duty ratio controller (refer Fig. 16). The flying capacitor voltage is balanced $V_{c_{1}}$ by using the switching state redundancies in mode 2 and mode 4 ($V_{AB}=0$ ). The charging and discharging modes of the capacitors are shown in Table 1.

TABLE 1 Charging Discharging Modes of Capacitors

FIGURE 16.

Control block diagram.

From the analysis in the previous section, it is clear that the switching frequency of the converter increases with a reduction in load (see Fig. 14a). To avoid these extreme high frequencies, the PI controller with limiter limits the converter’s switching frequency to 1.5 times the resonant frequency. Once the frequency controller reaches its maximum saturation, duty ratio control is used to regulate the output DC voltage. To decrease the output power, the duty ratio controller reduces the duty ratio (refer Fig. 14b). For this, error in DC bus voltage is replaced with output DC voltage error using a signal selector (refer Fig. 16). (Note: The DC bus voltage will not rise above the maximum reference value because the duty ratio of the converter is further reduced to reduce output power.)

The initial frequency of the controller is set at 1.5 times the resonant frequency. Both the frequency and duty ratio affects the output DC voltage. So for smooth operation, the frequency control loop is controlled very fast compared to the duty ratio control. Therefore for any changes in the load or input, the frequency controller shifts to its new frequency very fast. Duty ratio control loop slowly regulates the DC bus voltage and obtain necessary regulation. The discontinuous conduction mode of the proposed converter automatically shapes the average input current to be nearly sinusoidal and in-phase with the input voltage providing unity displacement power factor without any closed-loop control (See Fig. 6).

SECTION VII. Experimental Results

A 48V, 250W converter prototype is designed, and implemented. The converter ratings are: input supply voltage: 190-300 Vrms, output voltage: 48V, resonant frequency: 15kHz, DC bus voltage: 700-850 Vrms. Table 2 gives detailed converter parameters.

TABLE 2 Converter Parameters

The hardware is realized by using TMS320f28335 DSP processor as the controller. Output DC voltage, DC bus voltage, flying capacitor voltage and input supply voltage are sensed using voltage sensor LV-20P. A second-order butterworth low pass filter based on a high slew rate Op-amp MC34074 filters the feedback voltage signals. The hardware setup of the work is shown in Fig. 17.

FIGURE 17.

Experimental setup.

Fig. 18 shows the hardware result of source voltage and current at full load. These figures confirm the near unity power factor of the converter. Fig. 19 shows the discontinuous current through the input inductor $L_{in}$ . The input inductor current is filtered using an LC filter. The filtered waveform is in Fig. 18 Hardware results for flying capacitor and DC bus voltages are shown in Fig. 20 and 21. The flying capacitor voltage is held constant at half the DC bus voltage. The ripples in the capacitor voltages are very low. Fig. 22 shows the output DC voltage regulated at 48V. The ripple magnitude of output DC voltage is found to be less than 1%. The three-level voltage applied to LLC terminals $V_{AB}$ operating at a duty ratio of 70% is shown in Fig. 23.

FIGURE 18.

Source voltage and current waveform.

FIGURE 19.

Input current waveform through input inductor.

FIGURE 20.

Flying capacitor voltage waveform, $V_{C1}$ .

FIGURE 21.

DC bus voltage waveform, $V_{C1}+V_{C2}$ .

FIGURE 22.

Output DC voltage waveform, $V_{o}$ .

FIGURE 23.

Voltage waveform across LLC terminals, $V_{AB}$ .

Transient response of the DC bus voltage when the load is reduced by 30% from full load at instant A as shown in Fig. 24, where the capacitor voltage rises by 3% and settles to the reference bus voltage in 4.5 seconds. The variation in line current when 30% of the load is reduced from full load at the instant A is shown in Fig. 25. It is visible the current shifts to its new value without any transient overshoot. Fig. 26 shows the transient response of DC bus voltage when the DC bus controller is deactivated at instant A. The DC bus voltage comes into steady state within 3 sec once the control action is reinstated. This shows the effectiveness of the controller. The Fig. 27 shows the ZVS turn ON of switch $Q_{1}$ . The gate pulse to $Q_{1}$ is applied when the voltage across the switch $Q_{1}$ is zero, which confirms ZVS operation. All the four switches can be turned ON at ZVS.

FIGURE 24.

The transient response of DC Bus voltage when the load reduced by 30% of full load.

FIGURE 25.

The transient response of input supply current when the load reduced by 30% of full load.

FIGURE 26.

The transient response of DC Bus voltage when the DC bus controller is deactivated at instant A and reactivated at instant B.

FIGURE 27.

Voltage across switch $Q_{1}$ (green color) and its gate pulse (pink color).

The variation of duty ratio with load is depicted in Fig. 28. The proposed topology is capable of regulating DC bus voltage at a constant value in the region between 0%-100% of full load (see Fig. 29). Though the converter’s experimental power factor shows a very slight decrease with a decrease in load, the power factor is greater than 0.95 for load variation of 20% to 100% (refer Fig. 30).

FIGURE 28.

Duty ratio vs. percentage load.

FIGURE 29.

DC bus voltage vs. percentage load.

FIGURE 30.

Power factor vs. percentage load.

SECTION VIII. Conclusion

This paper has proposed a three-level flying capacitor based topology for AC/DC LLC resonant converters. The converter has a bridgeless topology which reduces the number of conducting devices. The controller uses a dual control scheme which varies duty ratio and frequency to regulate DC bus and output DC voltages respectively. The converter is designed to operate in discontinuous conduction mode to obtain a near unity power factor without having any active current control techniques. Furthermore, the topology provides low voltage stress, ZVS for all the four switches, and reduces losses. For verification, a 250W, 230V to 48V AC-DC converter prototype has been designed and implemented. The DC bus voltage is held constant at 750V with a peak overshoot of 3.3% even when the load is reduced by 30% from full load.

ACKNOWLEDGMENT

This article is an extension of the work presented in the conference paper “A Three-Level Half-Bridge Flying Capacitor Topology for Single-Stage AC-DC LLC Resonant Converter” [1]. This article was presented at the IEEE International Conference on Power Electronics Drives and Energy Systems (PEDES), December 2018.