Abstract:
In this paper, a high-speed 64-bit carry look-ahead adder is implemented by race logic for fast carry generation. G/sup 1/g/G/sup 1/k (Level 1 Group Generate/Kill) and G/...Show MoreMetadata
Abstract:
In this paper, a high-speed 64-bit carry look-ahead adder is implemented by race logic for fast carry generation. G/sup 1/g/G/sup 1/k (Level 1 Group Generate/Kill) and G/sup 2/g/G/sup 2/k (Level 2 Group Generate/Kill) stages are designed by race logic. The adder consists of 4-stages, and clk-S63 delay is 480 ps with 0.18 /spl mu/m CMOS technology.
Date of Conference: 14-16 June 2001
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:4-89114-014-3
Contents 