A Power Efficient ECG Front-End with Input-Adaptive Gain Reaching 67.6-dB Dynamic Range

For Electrocardiograph (ECG) detection, the analog front-end (AFE) needs to distinguish the signals with high amplitude fluctuation, in which normally an ADC with 10 to 12 bit resolution with high dynamic range (DR) is required. In this paper, an input-adaptive control logic is proposed and implemented, which enables AFE to regulate the gain of amplifier according to the amplitude of input signal, which enables an 8-bit SAR ADC reaching 67.6 dB DR near the common-mode level. This design relies on the powerful backend calibration process that the design difficulty of the analog end is converted to the digital back end, which is a good and practical way in nowadays. The proposed structure is implemented with a 0.18\ \mu\mathrm{m}$ standard CMOS process. Measurement results show that the SNDR remains basically unchanged when the input amplitude decreases by a range from 6 dB to 35 dB, and the DR is boosted by 20.3 dB compared with the conventional 8-bit SAR ADC. The ADC and extra control logic consume 8.4 nW under 1 V supply at a sampling rate of 500 S/s.