Pseudo-NMOS Logic Circuits using ITO-Stabilized ZnO TFTs

In this paper, the 2-input/3-input XORs and majority gate based on ITO TFT are presented. The proposed circuits have a new pseudo-NMOS design style with a controllable pull-up device, whose advantages include a high noise margin and a high switching speed. At 5 V power supply, its measured results showed that the maximum delays of 2-inputs XOR, 3-input XOR and majority gate in this style are 5.20 μs, 6.65 μs, and 5.85 μs, respectively. This indicates that the general TFT logic can be implemented in such a style and it can also support the probability to realize the large digital logic circuits with moderate frequency based on ITO-stabilized ZnO TFT.