BTI and Soft-Error Tolerant Voltage Bootstrapped Schmitt Trigger Circuit

This letter presents a novel BTI resilient voltage bootstrapped Schmitt trigger (VB-ST) circuit with improved noise margin, leakage power and rail-to-rail voltage. An only NMOS transistor is used in the proposed VB-ST circuit, which helps to reduce the aging effect specially Negative Bias Temperature Instability (NBTI) on the circuit. The reliability of the circuit is mainly analyzed by using the critical charge and soft error rate ratio (SERR), which indicates that the critical charge and SERR of the VB-ST circuit are improved by 6.31× and reduced by 84.0%, respectively as compared to the CMOS circuit at 0.4V supply voltage. For the reliable and robust proposed circuit design, the quality factor (QF) is used as a performance metric and observed that the proposed circuit has 144× improved QF as compared to the CMOS circuit.