A 72-nW 440-mV Time Register Using Stacked-NMOS-Switched Gated Delay Cell in Biomedical Applications

This paper presents a time register that uses a gated delay pipeline, to hold or propagate time information through the line by a stacked NMOS switch. The minimum supply voltage can be down to 440 mV, which is much lower than previous state-of-the-arts whose supply voltage is 1 V or higher, making this design beneficial for wearable/implantable devices in biomedical applications. The post-layout simulation performed in 65-nm CMOS technology confirms the function of the proposed time register at a conversion rate of 10 MSamples/s. The stacked-NMOS-switched architecture contributes to low leakage current, realizing low power consumption of 72 nW. In addition, the coefficient of determination, denoted R
²
, is 0.9956 in the linear input range of 4–11 ns, indicating good linearity.