Abstract:
We developed a method for analyzing boron penetration and gate depletion using N/sup +/ and P/sup +/ dual-gate PMOSFETs. N/sup +/ gate PMOSFETs, which are immune to boron...Show MoreMetadata
Abstract:
We developed a method for analyzing boron penetration and gate depletion using N/sup +/ and P/sup +/ dual-gate PMOSFETs. N/sup +/ gate PMOSFETs, which are immune to boron penetration and gate depletion, exhibited the threshold voltage shifts and fluctuation in P/sup +/ gate PMOSFETs. We found that V/sub th/ fluctuation in P/sup +/ gate PMOSFETs is dominated by boron penetration and that it is possible to select high-performance Gbit DRAM fabrication processes that are robust against V/sub th/ fluctuation.
Published in: ICMTS 2001. Proceedings of the 2001 International Conference on Microelectronic Test Structures (Cat. No.01CH37153)
Date of Conference: 19-22 March 2001
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:0-7803-6511-9