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A new method for analyzing boron penetration and gate depletion using dual-gate PMOSFETs for high performance G-bit DRAM design | IEEE Conference Publication | IEEE Xplore

A new method for analyzing boron penetration and gate depletion using dual-gate PMOSFETs for high performance G-bit DRAM design


Abstract:

We developed a method for analyzing boron penetration and gate depletion using N/sup +/ and P/sup +/ dual-gate PMOSFETs. N/sup +/ gate PMOSFETs, which are immune to boron...Show More

Abstract:

We developed a method for analyzing boron penetration and gate depletion using N/sup +/ and P/sup +/ dual-gate PMOSFETs. N/sup +/ gate PMOSFETs, which are immune to boron penetration and gate depletion, exhibited the threshold voltage shifts and fluctuation in P/sup +/ gate PMOSFETs. We found that V/sub th/ fluctuation in P/sup +/ gate PMOSFETs is dominated by boron penetration and that it is possible to select high-performance Gbit DRAM fabrication processes that are robust against V/sub th/ fluctuation.
Date of Conference: 19-22 March 2001
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:0-7803-6511-9
Conference Location: Kobe, Japan

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