A FPGA based intra-parallel architecture for PageRank graph processing

Acceleration of large-scale graph processing by FPGA has been proved an energy efficient method, especially in edge computation scenarios. FPGA acceleration of graph calculation includes inter partition parallel and intra partition parallel. In this paper, we focus on intra partition parallel and present a novel data selection network of less complexity. Moreover, by intra sub-graph compression, proper inter subgraph scheduling, and some initialization modules, we get our graph processing architecture. We test PageRank algorithm on data set of Twitter using the novel architecture. Experiment shows that the FPGA can support a data selection network of 128 processing units and has an effective processing ability of 51 edges per cycle and a throughput of up to 7650 Mega Traversed Edges PER Second (MTEPS), which results in a 3x throughput improvement and 1.5x DRAM bandwidth utilization rate improvement comparing with state-of-the-art design.