Contents 1 Introduction
Simulation-based functional verification is a crucial yet time-consuming step in modern electronic design automation flows [23]. In this step, a design is simulated with a large number of input stimuli, and signals are monitored to determine if coverage goals and/or functional requirements are met. For complex designs, each input stimulus typically spans a large number of clock cycles. Since exhaustive simulation is impractical for real designs, using “good quality” stimuli that result in adequate coverage of the system's runs in targeted corners is extremely important [10]. Constrained random verification, or CRV, [12], [29], [30], [39] offers a practical solution to this problem. In CRV, the user provides constraints to ensure that the generated stimuli are valid and also to steer the system towards bug-prone corners. To ensure diversity, CRV allows randomization in the choice of stimuli satisfying a set of constraints. This can be very useful when the exact inputs needed to meet coverage goals or to test functional requirements are not known [11], [29]. In such cases, it is best to generate stimuli such that the resulting runs are uniformly distributed in the targeted corners of its behavior space. Unfortunately, state-of-the-art CRV tools [1], [2], [27], [34], [38] do not permit such uniform random sampling of input stimuli. Instead, they allow inputs to be assigned random values from a constrained set at specific simulation steps. This of course lends diversity to the generated stimuli. However, it gives no guarantees on the distribution of the resulting system runs. In this paper, we take a first step towards remedying this problem. Specifically, we present a technique for generating input stimuli that guarantees uniform (or user-specified bias in) distribution of the resulting system runs.
