A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS

A folding voltage-to-time converter (VTC) is proposed for low-power time-based (TB) flash ADCs performing voltage-to-time-to-digital conversion. Conventional VTCs in TB flash ADCs generate multiple time outputs or have nonlinear conversion gain, resulting in a large power consumption in time-to-digital converters (TDCs) due to power-inefficient architectures using a lot of comparators. The proposed VTC generates a single time output with a large-and-linear conversion gain because the proposed VTC folds the whole voltage input range several times and each voltage-to-time conversion is defined within the voltage range reduced by folding. This allows the TDC power consumption to be reduced by using power-efficient architectures. Moreover, the VTC generates digital outputs as a result of the folding operation, thereby relaxing the resolution requirement of the TDC. A 7-bit TB ADC is implemented with a 4× folding VTC having a 2-bit digital output and a 5-bit pipelined TDC for high-speed low-power operation. A TB ADC fabricated in a 1-V 65-nm CMOS process achieves a 4-GS/s sampling frequency, 11.3-mW power consumption, a 34.58-dB SNDR, and a 64.5-fJ/conv.-step figure of merit (FoM).

I. Introduction

The demand for high-speed communications has increased rapidly with the emergence of cloud computing and the Internet of Things. Because of the large channel loss in high-speed data communications, interest in high-speed analog-to-digital converters (ADCs) for receivers using digital signal processing (DSP) has increased [1]. High-speed ADCs are implemented by time-interleaving the operations of sub-ADCs. Here, flash ADCs or successive approximation register (SAR) ADCs are widely used as sub-ADCs. SAR ADCs have the lowest energy consumption and the best figures of merit (FoMs) among single-channel ADCs. Time-interleaved SAR ADCs using multiple channels can achieve high-speed operation while maintaining low energy consumption. However, they require a high interleaving factor and highly advanced technology nodes to achieve operation speeds higher than 3 GS/s (Fig. 1). On the other hand, flash ADCs show the fastest conversion among single-channel ADCs. However, they consume a lot of energy because a lot of dynamic comparators (CMPs) operate simultaneously. To reduce energy consumption while maintaining high-speed operation for a single channel, time-based (TB) flash ADCs have been tried; so far, they have achieved FoMs below 100 fJ/conversion-step [2]–[13]. Fig. 1.

FoM comparison.