MLIP Cores: Designing Hardware Generators with Programmable Microarchitectural Mechanisms

The research addresses implementation of custom internal mechanisms of computational process management abstractly from application functionality in hardware design. Explicit allocation of “microarchitectural middleware” design level is proposed. The key design components used at this level are custom programmable and synthesizable execution kernels — “micro-language” IP (MLIP) cores. The supporting framework is being developed by the authors. Experimental designing based on MLIP approach has demonstrated significant (up to 63%) code reusability for hardware cores that do not have any common structural submodules but do share custom internal scheduling and synchronization mechanisms that are cross-cutting relative to the hardware cores structure.