An In-Comparator Aperture-Time Equalization in a 7-nm FinFET CMOS 40-Gb/s Receiver

This letter proposes an in-comparator aperture-time equalization scheme using the impulse response of a clocked comparator. The technique is applied in a wireline link receiver prototype, implemented in CMOS 7-nm FinFET technology. The proposed method controls the aperture properties of the slicers by shaping their impulse sensitivity functions. We demonstrate an aperture skew control range of 4.7 ps with 147-fs accuracy for NRZ signaling at 40 Gb/s. PAM4 signaling at 80 Gb/s is also showcased using the proposed technique. These results serve as a proof of concept for next-generation source-synchronous chip-to-chip dense I/O links where aperture-time skews could be fine adjusted inside each comparator.

I. Introduction

The next generation of I/O links imposes challenging specifications on data rate and power consumption, necessitating efficient and simple circuits for the tuning of analog parameters such as aperture-time mismatches. We propose to move the classical boundary of sampling time fine adjustment from the clock distribution into the comparator. In this letter, an impulse sensitivity function (ISF) modification scheme is implemented inside a two-stage comparator topology. Measurement results confirm its effectiveness in fine-tuning the aperture time of the comparators, which has so far been overlooked in modern receiver architectures. Furthermore, the proposed technique is applicable to analog-to-digital converters where comparators are directly used as sampling devices without any track-and-hold in front of them.