At Speed Testing Challenges and Solutions for 56Gbps and 112Gbps PAM4 SerDes

Margining Test with either internal or external loopback has become a popular Design for Test (DfT) feature in high-speed SerDes. These SerDes DfT-derived results are becoming more unreliable because SerDes devices are pushing the limits of process variability. In addition, implementing DfT at the high-speed side of a device introduces the age-old problem of performance degradation due to the added circuitry. Given that many of these devices have very little performance margin, it is problematic to cause even a small reduction in performance. This is becoming more apparent with new Ethernet SerDes pushing the 100Gbps data rate. As with most new technology, more efficient and targeted DfT and BIST will emerge once the failure mechanisms and process dependencies of the devices are better known. For now, functional and parametric testing for these SerDes is generally required to make end-users comfortable that these devices are performing to spec and relying on off chip features implementation. Additionally, new DfT techniques and new metrics are being introduced to ensure manufacturing of these products.

1. Introduction

High-speed SerDes interfaces are the gateway for data traffic and analysis on the cloud. To support the massive growth of data handling, the industry is gearing up to deploy 100Gbps for data center interconnect. 100 GE (4×25Gbps) has been a growing trend in Data Center, while 400 GE (4×100Gbps) started deployment in 2019 in Hyper Scale Networks. Figure 1 shows this Data Center migration trend. Figure 1:

Data center speed migration [1]