33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications

FPGAs are a suitable platform for implementing up-to-date machine learning algorithms and state-of-the-art AI applications including inference engines in embedded systems and training accelerators in cloud systems. Despite its short design turn-around time, the achievable performance is limited by the low area efficiency originating from field programmability [1]–[2]. Also, data transfer minimization in both amount and distance is essential for higher energy efficiency, but conventional FPGAs often require pipeline registers at SRAM and DSP I/0s to conceal long communication latency originating from non-uniform tile architecture. In pursuit of an energy-efficient FPGA platform for AI applications, a via-switch FPGA (VS-FPGA), whose programmability is attained by non-volatile via-switch crossbars in BEOL, has been proposed with the aim of utilizing FEOL fully for computing [3], but its silicon implementation is not presented yet. This work demonstrates the first implementation of VS-FPGA in 65nm CMOS and further demonstrates an AI-oriented FPGA architecture.