A Proof of Concept implementation of a RINA interior router using P4-enabled software targets

The lack of high-performance RINA implementations to date makes it hard to experiment with RINA as an underlay networking fabric solution for different types of networks, and to assess RINA's benefits in practice on scenarios with high traffic loads. Typically high performance router implementations require dedicated hardware support, in the form of FPGAs or specialized ASICs. The advance of hardware programmability during the last years have opened new possibilities when it comes to prototyping new networking technologies. In particular, the use of P4 for programmable ASICs holds great promise for developing a RINA router. This paper has carried out the first Proof of Concept (PoC) implementation of a RINA interior router using the P4 language and its associated open-source tools; deploying and testing the development using the P4 reference test software switch (BMv2).