Abstract:
We have designed optimal ate paring engine on BN curve over 254bit prime field in 65nm CMOS FDSOI process. Algorithm is broken down into 2nd extension of the prime field ...Show MoreMetadata
Abstract:
We have designed optimal ate paring engine on BN curve over 254bit prime field in 65nm CMOS FDSOI process. Algorithm is broken down into 2nd extension of the prime field (Fp2) and optimized for pipelined multiplier of Fp2, results in global optimum design. Measurement results demonstrate world fastest implementation of 33us paring time with as low as 94uJ per paring. Energy consumption can be minimized down to 13.7uJ per pairing for 490mV operation. The design consists of 2.8MG and 85% of functional units are active throughout the paring operation. The demonstrated results are promising to realize functional encryptions such like ID based encryption, attribute-based encryption and searchable encryption.
Published in: 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Date of Conference: 04-06 November 2019
Date Added to IEEE Xplore: 06 April 2020
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