I. Introduction
Thermal modeling is essential to reliability analysis and thermal management of power electronics [1]. With an increasing request for higher power density and lower parasitics in power electronic systems, a more compact power device packaging with multichips is a trend. One of the challenges that come with it is the thermal cross-coupling (TCC) effects among different semiconductor chips. Junction temperature of a chip is not only affected by its own power losses but also that of neighboring devices. Conventional one-dimensional (1-D) lumped models (e.g., Cauer and Foster models [2]) neglect the TCC effects, and might result in misleading results for multichip modules. Finite-element method can provide detailed thermal results, but it is restrained to a limited time span. Beyond multichip components, a power electronic system consisting of multiple components also has the TCC effects [3], [4].