Clock Tree Synthesis Techniques for Optimal Power and Timing Convergence in SoC Partitions

Physical design is the process of converting a circuit description at Register Transfer Level into the physical layout. It primarily focuses on timing, power and area optimization by applying different optimization techniques at each stage of the design. Clock Tree Synthesis (CTS) is an important step in physical design flow. CTS builds the clock tree by balancing the skew in the entire design for all the clocks present. The conventional flow of CTS is inefficient at many points due to the increasing complexity of Integrated Circuits as a result of changing technology nodes. This paper focuses on analyzing efficient CTS techniques for optimal power and timing convergence in SoC Partition. The methodologies adopted for CTS are Multisource Clock Tree Synthesis and Multibit Flip-Flop usage with Clock Tree awareness.