LUT Input Reordering to Reduce Aging Impact on FPGA LUTs

In this article, we propose a fine-grained FPGA aging mitigation method. Our method focuses on Look Up Tables (LUTs) on which Boolean functions are mapped. Based on our observations, for any configuration, even if it is carefully selected, a number of LUT transistors experience severe stress rates. Therefore, an algorithm is presented to select several alternative configurations for each LUT. Alternative configurations are obtained by LUT input reordering. These alternative configurations are rotationally loaded into the FPGA. Experimental results shows that our method achieves 263 and 14.1 percent Mean Time To Failure (MTTF) improvement for Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI), respectively. Additionally, due to changing only local routings, our method imposes up to 1 percent performance overhead to the systems.