Layout Optimization Design of Power IoT Chips

In 2019, the State Grid Corporation of China proposed that the important material basis for building a worldclass energy Internet enterprise is to build and operate "two networks" (ie, "Ubiquitous Power Internet of Things" and "Strong Smart Grid"). The construction of "two networks" requires the support of a large number of terminal devices, and all devices need to complete the functions of automatic data collection and calculation. The implementation of these functions is inseparable from the support of the chip. The layout design of integrated circuits is one of the key steps in chip design. A good layout design can effectively optimize the chip area, reduce the cost of the chip, and help improve the chip performance. This article will use our company’s finished chip layout design examples to explain how to achieve high security, low power consumption, high integration and low cost of power security chip from the levels of chip module layout and chip overall layout.

I. Introduction

The emergence of Power Internet of Things technology is the product of applying IoT technology to the smart grid, which is the result of the rapid development of electronic information and communication technology [1-4]. The generation of this technology will effectively improve the utilization efficiency of existing power infrastructure and communication facilities resources. Integrated circuit is an important development direction of the new generation of electrical information technology. High security, low power consumption, high integration and low cost are the basic requirements of the new generation of SOC chips [5-7]. Chip layout design is one of the key technologies of integrated circuits. A good layout design can effectively optimize the chip area and improve the chip integration to reduce costs [8-10]. This paper proposes some design methods to optimize chip performance from the perspective of chip layout.