I. Introduction
Relentless scaling of transistors and wires in advanced semiconductor technologies has not only resulted in major process-related challenges but has also imposed severe design challenges in the sub-5nm technology regime. Dimensional scaling of designs, today, has been made possible by (i) Front-End-of-Line (FEOL) and Back-End-of-Line (BEOL) pitch scaling, which worsens short-channel effects in transistors and increases wire/contact resistances; and, (ii) fin depopulation in standard cells, which causes degradation of transistor drive. To enable further area scaling in sub-5nm nodes, a novel approach of burying the power rails into the substrate (Fig. 1–3) has been proposed, which no longer requires reserving two routing tracks for power nets (e.g, VDD or VSS) in the standard cell area [1]. Additionally, these buried power rails (BPRs) can achieve a higher aspect ratio, thus, exhibiting lower resistance than local-level BEOL power rails [2]. However, the new characteristics and design-constraints of BPR require re-design and restructuring of the power delivery network that connects to it.