Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nm | IEEE Conference Publication | IEEE Xplore

Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nm


Abstract:

The technology of buried power rails and back-side power delivery has been proposed for future scaling enablement, beyond the 5nm technology node. This paper studies the ...Show More
Notes: As originally published text, pages or figures in the document were missing or not clearly visible. A corrected replacement file was provided by the authors.

Abstract:

The technology of buried power rails and back-side power delivery has been proposed for future scaling enablement, beyond the 5nm technology node. This paper studies the CPU design implications of power delivery in the context of these technologies. Employing standard VLSI design flows and sign-off techniques, we benchmark the power delivery designs and technology options using the Arm Cortex-A53 CPU at an imec 3nm technology node. DC and AC analyses of the resulting power delivery networks are presented for the various designs with buried power rails (with front-side and back-side power delivery) and compared to conventional designs without buried power rails. It is shown that buried rails with front-side power delivery can improve the worst-case IR drop from 70mV to 42mV (~1.7X reduction) while buried rails with back-side power delivery substantially reduce IR drop to 10mV (a 7X reduction).
Notes: As originally published text, pages or figures in the document were missing or not clearly visible. A corrected replacement file was provided by the authors.
Date of Conference: 07-11 December 2019
Date Added to IEEE Xplore: 13 February 2020
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Conference Location: San Francisco, CA, USA

I. Introduction

Relentless scaling of transistors and wires in advanced semiconductor technologies has not only resulted in major process-related challenges but has also imposed severe design challenges in the sub-5nm technology regime. Dimensional scaling of designs, today, has been made possible by (i) Front-End-of-Line (FEOL) and Back-End-of-Line (BEOL) pitch scaling, which worsens short-channel effects in transistors and increases wire/contact resistances; and, (ii) fin depopulation in standard cells, which causes degradation of transistor drive. To enable further area scaling in sub-5nm nodes, a novel approach of burying the power rails into the substrate (Fig. 1–3) has been proposed, which no longer requires reserving two routing tracks for power nets (e.g, VDD or VSS) in the standard cell area [1]. Additionally, these buried power rails (BPRs) can achieve a higher aspect ratio, thus, exhibiting lower resistance than local-level BEOL power rails [2]. However, the new characteristics and design-constraints of BPR require re-design and restructuring of the power delivery network that connects to it.

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