Self-heating Induced Variability and Reliability in Advanced Logic Devices and Circuits

Non-planar device structures such as FinFETs are widely used in advanced CMOS technology, the non-planar structures with confined narrow channel region and the low thermal conductivity of materials will prevent heat dissipation, resulting in a localized lattice temperature rise, named self-heating effect (SHE) [1]–[3]. The SHE not only causes transistors' and circuits' performance varability and degradation but also exacerbates degradation of transistors' reliability and leading to the reduction of circuit's lifetime, which becomes a significant challenge to device engineers and circuit designers [4]–[6]. Thus, the self-heating effect is one of the important issues in the semiconductor industry. For device optimization and circuit design, it is necessary to capture self-heating induced statistical variability and reliability during circuit operation. Normally, the worst-case analysis for SHE at device and circuit level is used to provide a thermal-aware design guide, however, it may cause an inaccurate estimation as self-heating can be different in actual circuit operation.