Research on a New Test Method for Through Silicon Via Channel | IEEE Conference Publication | IEEE Xplore

Research on a New Test Method for Through Silicon Via Channel


Abstract:

This paper focuses on the test method for through silicon via (TSV) in three-dimensional integrated circuits (3D ICs), proposes a double-sided probes structure test metho...Show More

Abstract:

This paper focuses on the test method for through silicon via (TSV) in three-dimensional integrated circuits (3D ICs), proposes a double-sided probes structure test method for directly measuring the characteristic parameter of the TSV channel. A double-sided probes structure testing tool is designed for a square low-resistance silicon TSV adapter board, and the insertion loss of the TSV channel is selected to verify this method. In order to test TSV channels of the square low-resistance silicon TSV adapter board accurately, the double-sided probes testing tool mainly includes anti-crushing design, self-balancing redundant design and precise positioning design. The feasibility of this scheme is proved by comparing the measuring insertion loss by network analyzer with the simulation result by HFSS software. Through the research in this paper, the double-sided probes test method is an important auxiliary method for studying TSV technology, which can be used to directly measure the relevant characteristic parameters of TSV channel mainly obtained by electromagnetic simulation at present.
Date of Conference: 21-23 October 2019
Date Added to IEEE Xplore: 05 December 2019
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Conference Location: Hangzhou, China

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