Process Modules for High-Density Interconnects in Panel-Level Packaging

Advanced packaging technologies like wafer-level fan-out and 3-D system-in-package (3-D SIP) are rapidly penetrating the market of electronic components. For cost reduction, one approach is the migration of processes from wafer to panel format, called panel-level packaging (PLP). In a consortium of partners from industry and research, advanced technologies for PLP are developed. The project aims for an integrated process flow for 3-D SIPs with chips embedded into an organic laminate matrix. At first, 6 mm × 6 mm chips (100 μm thickness) with Cu bumps (25-μm height, 110-μm pitch) are placed into cavities of a printed circuit board (PCB) core layer. They are embedded by vacuum lamination of thin organic films. The core is equipped with fiducials for local alignment and provides handling robustness. Developments aim for a final panel size of 600 mm × 600 mm (here 227 mm × 305 mm demonstrated). Onto the contact side of embedded chips, a 25-μm dielectric film is applied. The copper bumps are subsequently opened by plasma etching. By sputtering and electroplating of Cu, electrical contacts to the chips are formed without via opening. Highaspect-ratio vias as an element for vertical interconnects are formed by UV laser drilling. At via diameters of 17 μm, a drill hole depth of 74 μm was achieved (aspect ratio 4.4:1). Using a newly developed electrolyte, microvia filling was achieved for aspect ratios up to 4:1. With a newly developed direct imaging (DI) machine, 4-μm structures in a 7-μm dry film photoresist are formed. Adaptive imaging of a redistribution layer was realized.