Bent Routing Pattern for FPGA

Routing architecture design is crucial in the early exploration of FPGA fabrics. In the modern unidirectional routing architectures, the signal passes through a programmable switch while turning into the channel perpendicular to the current one at the intersections, which may lead to excessive turning switches in the routing paths and cause the high latency. Most of the researches focus on the routing topology where the wire segments span in either vertical or horizontal direction. In this paper, we propose the bent routing pattern, where the bent wire segments can span in both vertical and horizontal channels without passing through any turning switch. The bent routing topology is designed to keep the regularity and symmetry, and then evaluated by the enhanced VTR. To optimize the architecture with the bent routing pattern, we develop a stochastic searching method based on the simulated annealing algorithm. The results show that the architecture with the mixture of bent wires and straight wires can achieve 9% shorter critical path delay and 11% area-delay product savings on average compared to the architecture with only straight wires.

I. Introduction

Small area and low delay are key requirements in the architecture design of Field-Programmable Gate Arrays (FPGAs). Most of the critical path delay in FPGAs is due to the programmable interconnections between logic blocks [1]–[3]. In island-style FPGAs [1], the interconnections are implemented through wire segments and programmable switches. Since the number of switches dominates the delay of routing paths [4]–[6], redundant switches increase the critical path delay. To improve the performance, modern FPGAs use the mixed multi-length wire segments to reduce switches in the straight-line directions [7]–[10]. The multi-length wire segments are common in commercial FPGAs such as the wire segments of various lengths which span 2, 4, 5, 12, or 16 CLBs in the UltraScale FPGAs [11].