An 8-b 2b/cycle Asynchronous SAR ADC with Capacitive Divider Based RC-DAC

This paper presents a 2b/cycle asynchronous SAR ADC with a capacitive divider based RC-DAC. The new architecture reduces the number of capacitors and resistors, leading to a smaller die area and lower hardware cost. It also allows for a new timing scheme with a merged samplingconversion cycle to increase the conversion speed. An 8-b SAR ADC with the proposed architecture is designed in 180nm CMOS technology operating at sampling rate of 65MS/s. The postlayout simulation shows the proposed SAR ADC can achieve SNDR of 45.16dB at near-Nyquist frequency and occupies an active area of 0.045mm². The FOM under a 1.2V&1.8V supply voltage is 216fJ/conversion-step with power consumption of 2.07mW.