Efficient Hardware Implementation of 2D Convolution on FPGA for Image Processing Application

Most image processing algorithms are regional and two dimensional (2D) by nature. This implies that 2D convolver function has great consequences for image processing application. 2D Convolution filtering is a technique that can be used for an immense array of image processing objective some of which include that as images sharpening, image smoothing, edge detection, and texture analysis. Our main goal in this paper is to develop an efficient architecture for the 2D convolution using control blocks. Hardware implementation of this 2D algorithm can be realized by a reduced number of shift registers, multipliers, adders, and control blocks, thus leading to considerable hardware saving and fewer number LUTs. Simulations had done in Verilog and prototyped on devices technology of Xilinx Spartan 3E Field Programmable Gate Arrays (FPGA) platform. The proposed 2D convolution architecture approach significantly faster and maximum time required after clock time is less compared to the existing 2D convolution implementation. The hardware created with the proposed architecture will save a lot of computational time.