I. Introduction
Faults in DRAM cells are becoming ever more prevalent with new process technologies, causing the protection using Error Correcting Codes (ECC) to increase from strong ChipKill protection [7] to include a second layer of ECC on-chip [13]. This trend includes even mobile devices [21] and efforts to gain in energy efficiency could further multiply the soft error rates [2]. To apply more granular protection techniques than uniformly increasing ECC strength, such as dynamically adaptable ECC [27], it is necessary to quantify the risk associated with any data stored in memory.