C4 Compatible Ultra-Thick Cu On-chip Magnetic Inductor Architecture Integrated with Advanced Polymer/Cu Planarization Process

Inductor is an essential component in Integrated Voltage Regulator(IVR) which is strongly corresponding to the efficiency of power management. In 2018 ECTC, an on-chip solenoid inductor package integrated with high-permeability magnetic(MAG) film and two ultra-thick Cu trace was successfully demonstrated, which exhibits the benefits of higher inductance, lower resistance, and competitive packaging dimension [1]. Two ultra-thick Cu trace for coils of inductor device inevitably accompanies with higher topography that will induce some concerns on processes, one of them is like bubble defect from spin coating process of photo resist. On the other hand, uneven plan resulted from high topography will also cause poor co-planarity(COP) post bump formation, result in concerns like cold joint in assembly process. In order to resolve this hindrance, a polish process on polymer and Cu by chemical & mechanistic planarization (CMP) is introduced to improve the topography of the inductor package. In the paper, a key process issue, interface delamination, relating to CMP will be disclosed. And the key approach that is how to optimize Cu surface treatment and parameter of CMP process for delamination improvement will be focused. In short, we face a critical issue poor COP post bump formation that induced from high topography in ultra-thick Cu scheme. How to realize CMP process for planarization is a key and must be relied on optimization of key approaches for delamination. At last, compared to the air-core thick copper inductor package reported last year, the results show that CMP can improved COP around 3~5-fold, and have comparable performance of electric resistance before/post wafer level torture.