PoP LPDDR5 (6.4 Gbps) NTODT and 1-Tap DFE for Signal Integrity Enhancement

LPDDR5 SI (Signal Integrity) enhancements are presented by using non-target DRAM termination and 1-tap DFE. LPDDR5 interface was running at 6.4 Gbps data rate, 0.5V VDDQ (TT) and VOH= ~300mV (WRITES). Mobile SoC-DRAM system in PoP (Package-on-Package) configuration was analyzed. Non-target DRAM termination in a dual-rank system mitigates the reflections coming to the target DRAM leading to improved SI, ~7% UI improvement was observed. 1-tap DFE (Decision Feedback Equalizer) is also employed to reduce the ISI (Inter-Symbol Interference) due to reflections, ~2ps UI improvement was observed. SI components (crosstalk and ISI) and VdIVW show that VdIVW having big impact on the system timing. Additionally, decreasing CIO and VdIVW show significant improvement in eye-apertures.