Improved CMOS Analog Switch

An improved CMOS switch architecture allowing input voltage levels greater than the power supply as well as having a reduced R
_ON
variation with the voltage applied is described in this paper. For this type of switch the ON resistance variation with the input voltage, its dependency on the supply voltage, leakage currents, input voltage range, off-isolation and the required silicon area were analyzed. The proposed architecture was implemented in a 0.18μm CMOS process and its performance was verified by simulations.