Verilog-A based Behavioral Modeling of an FBMC Transmitter

In this paper a Verilog-A based behavioral modelling of a filter-bank multicarrier (FBMC) transmitter with the focus on the RF-DAC cores is presented. Multiple switching signals within the transmitter yield to a tremendous degradation in simulation performance. Because of that, the simulation of the entire system at transistor-level is time consuming. The abstracted model leads to a reduction in simulation time of up to 70% with only half of the memory usage compared to the original model by still getting sufficient results. Furthermore, a performance friendly and simple technique is presented to generate signals with equidistantly spaced frequencies with additional abstraction level to generate jitter and deterministic phase noise. Verilog-A has been used to design the models in combination with Spectre simulator to verify the results.