What’s in Space – Exploration and Improvement of Line/Space Defect Inspection of Fine-Pitch Redistribution Layer for Fan-Out Wafer Level Packaging

Advanced wafer level packaging is moving into high volume mobile and consumer electronics markets. Drivers for new packaging and integration schemes are lower-cost processes and the high count of interconnects. The different functional parts of a high-performance package are designed with high-density interconnects requiring multiple fine-pitch redistribution layers (RDL) to route and fan-out the tight pitch interconnects to the package level. Currently, high-density fan-out packages are evolving toward 1μm line/space and even beyond. Reducing RDL line and space widths creates challenges for the different process steps that are used to produce RDL, therefore the need for accurate and precise inline process control. This paper will elaborate on the fundamental requirements for defectivity and metrology of fine-pitch RDL processing. Defect inspection and measurements are performed on wafers containing fine-pitch RDL. Based on the correlation between electrical yield results and inspection and measurement data, improvements for the smallest RDL line/space sizes are proposed and validated to meet the requirements for defectivity and metrology of fine-pitch RDL.