Quantitative Analysis and Suppression Strategies of Dv/dt Induced Turn-on of Cascode GaN FETs in Half-bridge Circuits

Dv/dt induced turn-on is one of the instability issues for cascode GaN FETs. However, due to the complicated internal structure, little research focuses on the numerical analysis of false turn-on for cascode GaN FETs. This paper presents an accurate analytical calculation of the dv/dt induced gate-source voltage of cascode GaN FETs in half-bridge circuits. The precise expression of the maximum induced voltage is firstly derived and relative influential factors are analyzed. This work can serve as an effective criterion to identify whether the dv/dt induced voltage exceeds the threshold voltage of the cascode GaN FET, and provide corresponding measures to avoid the false turn-on and ensure the safe operation. Simulation results well validate the theoretical calculation and analysis.