Micro-Transformer-Based Integrated Digital Isolator in 180/90 nm CMOS

An integrated circuit of a digital isolator comprising a transceiver chip implemented in standard 180 nm CMOS process as well as micro-transformers implemented in a special 90 nm technology is presented. The coreless transformer placed on a separate chip has a stacked structure with two adjacent planar copper windings in two layers separated by a silicon dioxide insulator. The transceiver utilizes a pulse edges encoding technique for transmitting signals through the insulation barrier. The proposed digital isolator has a feature in the topology of the elements, which ensures tolerance to the effects of ionizing radiation, as well as the small size of transformers, which makes it possible to create multichannel integrated circuits in small-sized packages. The tested prototype of the digital isolator provided a data transfer rate of more than 30 Mbps. As much as 2.5 kV isolation voltage is achieved between the coils of transformer.