Hot Carrier Reliability Improvement of Thicker Gate Oxide nFET Devices in Advanced FinFETs

Impact of process choices in terms of work function (WF) tuning and junction implant energy optimization for hot carrier (HCI) reliability in advanced FINFET technology is discussed here. The work focuses on understanding the nature and location of defects generated under different process conditions. Experimental observations are confirmed here with TCAD based simulations. For the first time, it is observed that maximum substrate current increases as stress progresses in contrast to traditional HCI mechanisms. To reduce HCI degradation, in addition to junction optimization, an additional knob is available in scaled FETs is the WF optimization, which can provide significant HCI reliability relief.