Heterogeneous SoC Integration with EMIB

The challenges of yielding larger Silicon dies increases as the technology node shrinks. IP availability on the same technology node on the same industry process is also not always possible because of design complexity, features and schedule. This necessitates integration of smaller manageable dies from different processes and fabs to create SiPs. Integration of chiplets on the package is the trend to sustain performance across multiple generations of chip design. This work highlights the role of EMIB (Embedded Multi-Tile Interconnect Bridge) for heterogeneous silicon integration.