Architecturally Compressed CNN: An Embedded Realtime Classifier (NXP Bluebox2.0 with RTMaps)

The convolution neural networks have revolutionized the computer vision domain. It has proven to be a dominant technology to carry out tasks such as image classification, semantic segmentation, and object detection. The convolution neural networks surpass the performance of the existing algorithms such as SIFT, HOG, etcetera. Where, instead of manually engineering the features, supervised learning help to learn the essential low-level and high-level features necessary for classifications. The convolution neural networks have become a popular tool to counter computer vision problems. However, it is computationally, and memory intensive to train and deploy the network because of the model size of a deep convolution neural networks. However, the research in the field of design space exploration (DSE) of neural networks and compression techniques to develop compact architectures, have made convolution neural networks memory and computationally efficient. These techniques have also improved the feasibility of convolution neural network for deployment on embedded targets. The paper explores the concept of compact convolution filters to reduce the number of parameters in a convolution neural network. The intuition behind the approach is that replacing convolution filters with a stack of compact convolution filters helps in developing a compact architecture with competitive accuracy. This paper explores the fire module a compact convolution filter and proposes a method of recreating a state-of-the-art architecture VGG-16 using the fire modules to develop a compact architecture, which is further trained on the CIFAR-10 dataset and deployed on a real-time embedded platform known as Bluebox 2.0 by NXP using RTMaps software framework.

I. Introduction

Since the proposition of the convolution neural networks, the field of deep learning has experienced an exponential growth, focussing on various aspects of deep learning such as defining new architectures like RESNET [5], Squeezenet [1], VGG16, VGG19 [2], developing new optimization techniques, various training methodology and implementation of non-linearity like ReLU, ELU, to combat optimization problems. These developments have substantially aided in training a deeper neural network for image recognition or object detection challenge. The increase in the depth of the neural networks has also led to accelerated development of various hardware architectures such as graphics processing unit, tensor processing unit and large-scale distributed deep networks [3], which uses parallel architectures and multiple computation units. The boards such as S32V234, Bluebox 2.0 (embedded systems) by NXP NVIDIAs TITAN, TESLA, GTX 1080(GPUs) and Jetson TK1(embedded systems) are widely being used for deploying and accelerating training process of various deep convolution neural networks.