A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

The graphic DRAM standard GDDR6 is developed to overcome the limitation of previous standards GDDR5/5X for achieving high-speed operation. This paper introduces 16-Gb GDDR6 DRAM with a per-bit trainable single-ended decision feedback equalizer (DFE), a reference impedance (ZQ)-coded transmitter, and a phase-locked loop (PLL)-less clocking to overcome I/O speed limitation by the DRAM process. Furthermore, this paper optimizes clock- and power-domain crossings and adopts split-die architecture to improve signal integrity (SI). This GDDR6 operates 16 Gb/s/pin with 1.15 V and achieves 18 Gb/s/pin with 1.35 V in the DRAM process.

I. Introduction

Since GDDR3 [1], [2] was developed for high-performance graphics and multimedia, the graphic DRAM was evolved to increase total bandwidth in a short time about couple of years through GDDR4 [3] to GDDR5. After issuing GDDR5 standard, GDDR5’s speed and density have been steadily developing for about 10 years from 6 to 9 Gb/s/pin and from 512 Mb to 8 Gb [4]–[8], respectively, as shown in Fig. 1. Fig. 1.

GDDR speed and density trend.