A bulk 65nm Cortex-M0+ SoC with All-Digital Forward Body Bias for 4.3X Subthreshold Speedup

IoT devices demand ultra-low power operation while still achieving the performance demanded by application constraints. Dynamic forward body biasing can help to achieve this by providing a speed-up during active operation without incurring a leakage penalty' during standby periods. While body biasing has been fully explored in FD-SoI technology, bulk CMOS can also benefit from efficient forward body biasing. At subthreshold voltage levels, the Low Voltage Swapped Body (LVSB) technique, in which n-well and p-well are driven to VSS and VDD respectively, helps to realize a significant speedup without incurring analog bias generation overheads. This work presents key advances to leverage LVSB, proven on a bulk 65nm subthreshold Arm Cortex-M0+ system. The system achieves a 4.3X speedup on the ULPBench benchmark at a cost of only 11% average power and 10.4% area, while showing that LVSB can be usefully applied up to 0.50V.

I. Introduction

The energy efficiency demands of IoT devices are driving renewed interest in subthreshold systems [1]-[3]. However, reduced performance is a major barrier to adoption. Fine-grained VDD control or analog body bias are commonly used to improve performance at the expense of area, energy and complexity. Low Voltage Swapped Body (LVSB) is a performance boosting technique introduced in [5], in which n-well and p-well may be "swapped" to power and ground rails respectively as long as the device is operating below the substrate latch-up voltage (Fig. 1). This provides a large forward body bias to both n and p devices, which translates to a significant speedup. Prior work [4]-[6] applied LVSB primarily to standalone logic blocks and reported speed increases of up to 3.7×.