A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18- $\mu$ m CMOS

A new solution for an ultralow-voltage bulkdriven (BD) asynchronous delta-sigma modulator is described in this paper. While implemented in a standard 0.18-μm CMOS process from the Taiwan Semiconductor Manufacturing Company and supplied with VDD = 0.3 V, the circuit offers a 53.3-dB signal-to-noise and distortion ratio, which corresponds to 8.56-bit resolution. In addition, the total power consumption is 37 nW, the signal bandwidth is 62 Hz, and the resulting power efficiency is 0.79 pJ/conversion. The above-mentioned features have been achieved employing a highly linear transconductor and a hysteretic comparator based on nontailed BD differential pair.