From Low-Power to No-Power: Adaptive Clocking for Event-Driven Systems

Reduction of power consumption of digital systems is a major concern especially in modern smart sensor systems. These systems are often only activated on request and their power consumption is therefore dominated by the idle-mode. Power reduction mechanisms such as clock or power gating reduce the activity or leakage in the purely digital circuits. We propose a novel adaptive clocking scheme that optimizes the energy demand using a fine-grained oscillator control on cycle-level. To evaluate our new approach, we analytically analyze the power consumption of the regarded system in comparison with available methods. The power of our new adaptive clocking is shown in an integrated smart sensor for capacitive measurements working in a passive wireless sensor node. Using our methods, we show that the energy demand of the example system is reduced even in the case of continuous measurements that demand for a high activity in the digital circuitry.

I. Introduction

Digital systems are mostly clocked to ensure correct timing behavior. The fundamental time unit used in RTL design is the clock cycle. This concept imposes several challenges. The distribution of the clock signal in a synthesized circuit is usually done by a carefully constructed clock tree [1]. This structure ensures the in-time arrival of the clock signal at each depending element. Due to its high gate-count and activity, it contributes significantly to the power consumption of the overall circuit.