Dynamic Inside-Out Verification Using Inverse Transactions in TLM

With growing design complexity, the reuse of module and subsystem level verification knowledge on electronic system level (ESL) becomes more and more challenging. The “Portable Stimulus Specification Working Group” intends to offer solutions such as stimuli reuse for today's verification challenges. This paper proposes a novel Inside-Out Verification (IOV) methodology, which makes module level dynamic verification knowledge highly reusable on system level by using transactions and inverse transactions. IOV can be combined with System Verilog based UVM. The examples in this paper are based on PDVL (a super-sub-set of SystemVerilog) and SystemC.

I. Introduction

An ESL verificationist needs to understand the design functionality, how to drive and to monitor the design behavior and how to pass information/data through a complex electronic system. Another challenge is, that the defined (cross-)coverage points must be hit during the dynamic verification runs. These tasks get increasingly challenging with rising design complexity. The research field to automate this process is called automatic functional pattern generation (AFPG). From the industry's perspective, the universal verification methodology (UVM, [1]) has become the standard testbench environment, according to Foster in [2].