High-Speed and Hardware-Efficient Successive Cancellation Polar-Decoder

This brief presents an algorithm for the processing element (PE) of polar decoder based on 2's complement representation of logarithmic likelihood ratios. It simplifies computation and alleviates critical path delay of PE. In addition, we propose a low complexity algorithm and p-node architecture for 2-bits successive-cancellation (SC) polar-decoding scheme. Furthermore, overall SC polar decoder-architecture has been design by incorporating suggested PE architectures as well as p-nodes to support code-length and code-rate (r) of 1024 bits and 1/2, respectively. We have synthesized and post-layout simulated our design in UMC 180-nm CMOS process and it occupies an area of 6.1 mm² and operates at a maximum clock frequency of 446 MHz. Our decoder delivers a throughput of 298r Mb/s which is 16% better than the state-of-the-art implementation. It has achieved better throughput efficiency of 1.01r compared to recently reported works.