Abstract:
The paper proposes an architecture of a high-speed regular expression (RE) matching system with fast updates of an RE set. The architecture uses highly memory-efficient D...Show MoreMetadata
Abstract:
The paper proposes an architecture of a high-speed regular expression (RE) matching system with fast updates of an RE set. The architecture uses highly memory-efficient Delayed Input DFAs (D2FAs), which are organized to a processing pipeline. The architecture is designed so that it communicates only locally among its components in order to achieve high frequency even for a large number of parallel matching engines (MEs), which allows scaling throughput to hundreds of gigabits per second (Gbps). The architecture is able to achieve processing throughput of up to 400 Gbps on current FPGA chips.
Published in: 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
Date of Conference: 29 April 2018 - 01 May 2018
Date Added to IEEE Xplore: 11 September 2018
ISBN Information:
Electronic ISSN: 2576-2621