Exploring Network on Chip Architectures Using GEM5

The number of computing resources in a SoC (System on a Chip) has been steadily increasing to meet greater computational requirements in a shorter time. However, associated problems that have cropped up with these increased number of resources also need to be addressed. In this work, we have made a comparative study of simple and Garnet networks on these SoCs using both mesh and crossbar topologies in each. We have seen that mesh is better than crossbar for both simple and garnet networks, but in mesh performance degrades as the size of network increases. Furthermore, a detailed study of standard cache coherence protocols has also been made with the help of MI and MESI_Two_Level and MOESI_CMP protocols. The simulator we have used for this study is GEM5 and the benchmark used is SPLASH2. We have observed that performance measured in form of computation time has increased from MI to MESI_Two_Level to MOESI_CMP.